advanced and ever advancing mitsubishi electric mitsubishi 8-bit single-chip microcomputer 740 family / 38000 series 38b5 group users manual mitsubishi electric
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preface this users manual describes mitsubishis cmos 8- bit microcomputers 38b5 group. after reading this manual, the user should have a through knowledge of the functions and features of the 38b5 group, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. for details of software, refer to the 740 family software manual. for details of development support tools, refer to the development support tools for microcomputers data book.
before using this users manual this users manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. organization l chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. l chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. l chapter 3 appendix this chapter includes a list of registers, and necessary information for systems development using the microcomputer, the mask rom confirmation (for mask rom version), rom programming confirmation, and the mark specifications which are to be submitted when ordering. 2. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: 2: bit attributesthe attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is arranged name functions at reset rw b 0 1 2 3 4 0 0 0 0 0 5 5 5 6 7 0 b0 b1 b2 b3 b4 b5 b6 b7 contents immediately after reset release bit attributes (note 1) 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : processor mode bits stack page selection bit nothing arranged for these bits. these are write disabled bits. when these bits are read out, the contents are ?. fix this bit to ?. main clock division ratio selection bits not available b1 b0 0 : 0 page 1 : 1 page 0 0 : f = x in /2 (high-speed mode) 0 1 : f = x in /8 (middle-speed mode) 1 0 : f = x in /8 (middle-speed mode) 1 1 : f = x in (double-speed mode) : bit that is not used for control of the corresponding function 0 notes 1: contents immediately after reset release 0??at reset release 1??at reset release undefinedundefined or reset release contents determined by option at reset release [ rread read enabled 5 read disabled wwrite write enabled 5 write disabled (note 2) cpu mode register (cpum) [address : 3b 16 ] bits 1 b7 b6 0
i 38b5 group users manual table of contents table of contents chapter 1 hardware description ............................................................................................................................... . 1-2 features ............................................................................................................................... ..... 1-2 application ............................................................................................................................... . 1-2 pin configuration .................................................................................................................. 1-2 functional block .................................................................................................................. 1-3 pin description ........................................................................................................................ 1-4 part numbering ....................................................................................................................... 1-6 group expansion .................................................................................................................... 1-7 memory type ............................................................................................................................ 1-7 memory size ............................................................................................................................. 1- 7 package ............................................................................................................................... ...... 1-7 functional description ...................................................................................................... 1-8 central processing unit (cpu) .............................................................................................. 1-8 memory ............................................................................................................................... ..... 1-12 i/o ports ............................................................................................................................... ... 1-14 interrupts ............................................................................................................................... .. 1-20 timers ............................................................................................................................... ....... 1-23 serial i/o ............................................................................................................................... .. 1-28 fld controller ........................................................................................................................ 1-40 a-d converter ......................................................................................................................... 1-52 pulse width modulation (pwm) ........................................................................................... 1-53 interrupt interval determination function ............................................................................ 1-56 watchdog timer ..................................................................................................................... 1-58 buzzer output circucit .......................................................................................................... 1-59 reset circuit ........................................................................................................................... 1-60 clock generating circuit ....................................................................................................... 1-62 notes on programming ..................................................................................................... 1-65 notes on use .......................................................................................................................... 1-65 data required for mask orders ................................................................................ 1-66 data required for rom writing orders ................................................................. 1-66 rom programming method .............................................................................................. 1-66 mask option of pull-down resistor ......................................................................... 1-67 functional description supplement ......................................................................... 1-69 chapter 2 application 2.1 i/o port ............................................................................................................................... ...... 2-2 2.1.1 memory assignment ....................................................................................................... 2-2 2.1.2 relevant registers .......................................................................................................... 2-3 2.1.3 terminate unused pins .................................................................................................. 2-6 2.1.4 notes on use .................................................................................................................. 2-7 2.1.5 termination of unused pins .......................................................................................... 2-8 2.2 timer ............................................................................................................................... ........ 2-10 2.2.1 memory map ................................................................................................................. 2-10 2.2.2 relevant registers ........................................................................................................ 2-11
ii 38b5 group users manual table of contents 2.2.3 timer application examples ........................................................................................ 2-19 2.3 serial i/o ............................................................................................................................... . 2-35 2.3.1 memory map ................................................................................................................. 2-35 2.3.2 relevant registers ........................................................................................................ 2-36 2.3.3 serial i/o1 connection examples ............................................................................... 2-47 2.3.4 serial i/o1s modes ..................................................................................................... 2-49 2.3.5 serial i/o1 application examples ............................................................................... 2-50 2.3.6 serial i/o2 connection examples ............................................................................... 2-56 2.3.7 serial i/o2s modes ..................................................................................................... 2-58 2.3.8 serial i/o2 application examples ............................................................................... 2-59 2.3.9 notes on serial i/o1 .................................................................................................... 2-78 2.3.10 notes on serial i/o2 .................................................................................................. 2-80 2.4 fld controller ...................................................................................................................... 2-83 2.4.1 memory assignment ..................................................................................................... 2-83 2.4.2 relevant registers ........................................................................................................ 2-84 2.4.3 fld controller application examples ......................................................................... 2-93 2.4.4 notes on use .............................................................................................................. 2-124 2.5 a-d converter ..................................................................................................................... 2-125 2.5.1 memory assignment ................................................................................................... 2-125 2.5.2 relevant registers ...................................................................................................... 2-125 2.5.3 a-d converter application examples ........................................................................ 2-129 2.5.4 notes on use .............................................................................................................. 2-131 2.6 pwm ............................................................................................................................... ....... 2-132 2.6.1 memory assignment ................................................................................................... 2-132 2.6.2 relevant registers ...................................................................................................... 2-132 2.6.3 pwm application example ......................................................................................... 2-134 2.6.4 notes on use .............................................................................................................. 2-135 2.7 interrupt interval determination function ..................................................................... 2-136 2.7.1 memory assignment ................................................................................................... 2-136 2.7.2 relevant registers ...................................................................................................... 2-136 2.7.3 interrupt interval determination function application examples ............................ 2-140 2.8 watchdog timer .................................................................................................................. 2-144 2.8.1 memory assignment ................................................................................................... 2-144 2.8.2 relevant register ........................................................................................................ 2-144 2.8.3 watchdog timer application examples ..................................................................... 2-145 2.8.4 notes on use .............................................................................................................. 2-146 2.9 buzzer output circuit ........................................................................................................ 2-147 2.9.1 memory assignment ................................................................................................... 2-147 2.9.2 relevant register ........................................................................................................ 2-147 2.9.3 buzzer output circuit application examples ............................................................ 2-148 2.10 reset circuit ..................................................................................................................... 2-149 2.10.1 connection example of reset ic ............................................................................ 2-149 2.10.2 notes on use ............................................................................................................ 2-150 2.11 clock generating circuit ................................................................................................ 2-151 2.11.1 relevant register ...................................................................................................... 2-151 2.11.2 clock generating circuit application examples ..................................................... 2-152
iii 38b5 group users manual table of contents chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 absolute maximum ratings ............................................................................................ 3-2 3.1.2 recommended operating conditions ............................................................................ 3-3 3.1.3 electrical characteristics ................................................................................................ 3-4 3.1.4 a-d converter characteristics ....................................................................................... 3-5 3.1.5 timing requirements and switching characteristics ................................................... 3-6 3.2 standard characteristics ...................................................................................................... 3-8 3.2.1 power source current standard characteristics .......................................................... 3-8 3.2.2 port standard characteristics ........................................................................................ 3-9 3.2.3 a-d conversion standard characteristics ................................................................... 3-13 3.3 notes on use ........................................................................................................................ 3-14 3.3.1 notes on interrupts ...................................................................................................... 3-14 3.3.2 notes on serial i/o1 .................................................................................................... 3-15 3.3.3 notes on serial i/o2 .................................................................................................... 3-16 3.3.4 notes on fld controller .............................................................................................. 3-19 3.3.5 notes on a-d converter .............................................................................................. 3-19 3.3.6 notes on pwm ............................................................................................................. 3-19 3.3.7 notes on watchdog timer ............................................................................................ 3-20 3.3.8 notes on reset circuit .................................................................................................. 3-20 3.3.9 notes on input and output pins ................................................................................. 3-20 3.3.10 notes on programming .............................................................................................. 3-22 3.3.11 programming and test of built-in prom version ................................................... 3-23 3.3.12 notes on built-in prom version .............................................................................. 3-24 3.3.13 termination of unused pins ...................................................................................... 3-25 3.4 countermeasures against noise ...................................................................................... 3-26 3.4.1 shortest wiring length .................................................................................................. 3-26 3.4.2 connection of bypass capacitor across v ss line and v cc line ............................... 3-28 3.4.3 wiring to analog input pins ........................................................................................ 3-29 3.4.4 oscillator concerns ....................................................................................................... 3-29 3.4.5 setup for i/o ports ....................................................................................................... 3-31 3.4.6 providing of watchdog timer function by software .................................................. 3-32 3.5 control registers .................................................................................................................. 3-33 3.6 mask rom confirmation form ........................................................................................... 3-67 3.7 rom programming confirmation form ............................................................................ 3-75 3.8 mark specification form ..................................................................................................... 3-77 3.9 package outline ................................................................................................................... 3-78 3.10 list of instruction code ................................................................................................... 3-79 3.11 machine instructions ........................................................................................................ 3-80 3.12 m35501fp ............................................................................................................................ 3-9 1 3.13 sfr memory map ............................................................................................................ 3-103 3.14 pin configuration ............................................................................................................. 3-104
i 38b5 group user?s manual list of figures list of figures chapter 1 hardware fig. 1 pin configuration of m38b5xmxh-xxxxfp ..................................................................... 1-2 fig. 2 functional block diagram ................................................................................................... 1-3 fig. 3 part numbering .................................................................................................................... 1-6 fig. 4 memory expansion plan ..................................................................................................... 1-7 fig. 5 740 family cpu register structure ................................................................................... 1-8 fig. 6 register push and pop at interrupt generation and subroutine call ........................... 1-9 fig. 7 structure of cpu mode register ..................................................................................... 1-11 fig. 8 memory map diagram ...................................................................................................... 1-12 fig. 9 memory map of special function register (sfr) .......................................................... 1-13 fig. 10 structure of pull-up control registers (pull1 and pull2) ...................................... 1-14 fig. 11 port block diagram (1) ................................................................................................... 1-17 fig. 12 port block diagram (2) ................................................................................................... 1-18 fig. 13 port block diagram (3) ................................................................................................... 1-19 fig. 14 interrupt control ............................................................................................................... 1-22 fig. 15 structure of interrupt related registers ........................................................................ 1-22 fig. 16 structure of timer related register ................................................................................ 1-23 fig. 17 block diagram of timer .................................................................................................. 1-24 fig. 18 timing chart of timer 6 pwm 1 mode ........................................................................... 1-25 fig. 19 block diagram of timer x .............................................................................................. 1-27 fig. 20 structure of timer x related registers .......................................................................... 1-27 fig. 21 block diagram of serial i/o1 ......................................................................................... 1-28 fig. 22 structure of serail i/o1 control registers 1, 2 ............................................................ 1-29 fig. 23 structure of serial i/o1 control register 3 ................................................................... 1-30 fig. 24 structure of serial i/o1 automatic transfer data pointer ........................................... 1-31 fig. 25 automatic transfer serial i/o operation ....................................................................... 1-32 fig. 26 s stb1 output operation .................................................................................................... 1-33 fig. 27 s busy1 input operation (internal synchronous clock) ................................................... 1-33 fig. 28 s busy1 input operation (external synchronous clock) .................................................. 1-33 fig. 29 s busy1 output operation (internal synchronous clock, 8-bits serial i/o) ................... 1-34 fig. 30 s busy1 output operation (external synchronous clock, 8-bits serial i/o) .................. 1-34 fig. 31 s busy1 output operation in automatic transfer serial i/o mode (internal synchronous clock, s busy1 output function outputs each 1-byte) ................................................... 1-34 fig. 32 s rdy1 output operation .................................................................................................... 1-35 fig. 33 s rdy1 input operation (internal synchronous clock) .................................................... 1-35 fig. 34 handshake operation at serial i/o1 mutual connecting (1) ...................................... 1-36 fig. 35 handshake operation at serial i/o1 mutual connecting (2) ...................................... 1-36 fig. 36 block diagram of clock snchronous serial i/o2 ......................................................... 1-37 fig. 37 operation of clock synchronous serial i/o2 function ................................................ 1-37 fig. 38 block diagram of uart serial i/o2 ............................................................................. 1-38 fig. 39 operation of uart serial i/o2 function ...................................................................... 1-38 fig. 40 structure of serial i/o2 related register ...................................................................... 1-39 fig. 41 block diagram for fld control circuit .......................................................................... 1-40 fig. 42 structure of fldc mode register ................................................................................. 1-41 fig. 43 segment/digit setting example ..................................................................................... 1-42 fig. 44 fld automatic display ram assignment .................................................................... 1-43 fig. 45 example of using fld automatic display ram in 16-timingordinary mode ......... 1-44
ii 38b5 group users manual list of figures fig. 46 example of using fld automatic display ram in 16-timing?gradation display mode ............................................................................................................................... ......................... 1-45 fig. 47 example of using fld automatic display ram in 32-timing mode ......................... 1-46 fig. 48 structure of fldram write disable register ............................................................... 1-47 fig. 49 example of digit timing using grid scan type ............................................................. 1-48 fig. 50 example of using fld automatic display ram using grid scan type .................... 1-48 fig. 51 fldc timing .................................................................................................................... 1-50 fig. 52 p8 4 to p8 7 fld output waveform ................................................................................. 1-51 fig. 53 structure of port p8 fld output control register ....................................................... 1-51 fig. 54 structure of a-d control register .................................................................................. 1-52 fig. 55 black diagram of a-d converter ................................................................................... 1-52 fig. 56 pwm block diagram ....................................................................................................... 1-53 fig. 57 pwm timing ..................................................................................................................... 1-54 fig. 58 structure of pwm control register ............................................................................... 1-55 fig. 59 14-bit pwm timing .......................................................................................................... 1-55 fig. 60 interrupt interval determination circuit block diagram ............................................... 1-56 fig. 61 structure of itnerrupt interval determination control register .................................... 1-57 fig. 62 interrupt inteval determination operation example (at rising edge active) ............. 1-57 fig. 63 interrupt interval determination operation example (at both-sided edge active) ... 1-57 fig. 64 block diagram of watchdog timer ................................................................................. 1-58 fig. 65 structure of watchdog timer control register .............................................................. 1-58 fig. 66 block diagram of buzzer output circuit ........................................................................ 1-59 fig. 67 structure of buzzer output control register ................................................................ 1-59 fig. 68 reset circuit example .................................................................................................... 1-60 fig. 69 reset sequence .............................................................................................................. 1-60 fig. 70 internal status at reset .................................................................................................. 1-61 fig. 71 ceramic resonator circuit .............................................................................................. 1-62 fig. 72 external clock input circuit ............................................................................................ 1-62 fig. 73 clock generating circuit block diagram ....................................................................... 1-63 fig. 74 state transitions of system clock ................................................................................. 1-64 fig. 75 programming and testing of one time prom version ............................................ 1-66 fig. 76 digit timing waveform (1) .............................................................................................. 1-67 fig. 77 digit timing waveform (2) .............................................................................................. 1-68 fig. 78 timing chart after interrupt occurs ............................................................................... 1-70 fig. 79 time up to execution of interrupt processing routine ............................................... 1-70 fig. 80 a-d conversion equivalent circuit ................................................................................. 1-72 fig. 81 a-d conversion timing chart .......................................................................................... 1-72 chapter 2 application fig. 2.1.1 memory assignment of i/o port relevant registers .................................................. 2-2 fig. 2.1.2 structure of port pi (i = 0, 1, 2, 3, 4, 5, 7, 8) ........................................................ 2-3 fig. 2.1.3 structure of port p6 ..................................................................................................... 2-3 fig. 2.1.4 structure of port p9 ..................................................................................................... 2-3 fig. 2.1.5 structure of port pi (i = 0, 2, 4, 5, 7, 8) direction register ................................... 2-4 fig. 2.1.6 structure of port p6 direction register ...................................................................... 2-4 fig. 2.1.7 structure of port p9 direction register ...................................................................... 2-5 fig. 2.1.8 structure of pull-up control register 1 ....................................................................... 2-5 fig. 2.1.9 structure of pull-up control register 2 ....................................................................... 2-6 fig. 2.2.1 memory map of registers relevant to timers .......................................................... 2-10
iii 38b5 group users manual list of figures fig. 2.2.2 structure of timer i (i=1, 3, 4, 5, 6) ....................................................................... 2-11 fig. 2.2.3 structure of timer 2 .................................................................................................. 2-11 fig. 2.2.4 structure of timer 6 pwm register ......................................................................... 2-11 fig. 2.2.5 structure of timer 12 mode register ....................................................................... 2-12 fig. 2.2.6 structure of timer 34 mode register ....................................................................... 2-12 fig. 2.2.7 structure of timer 56 mode register ....................................................................... 2-13 fig. 2.2.8 structure of timer x (low-order, high-order) .......................................................... 2-13 fig. 2.2.9 structure of timer x mode register 1 ..................................................................... 2-14 fig. 2.2.10 structure of timer x mode register 2 ................................................................... 2-15 fig. 2.2.11 structure of interrupt request register 1 ............................................................... 2-16 fig. 2.2.12 structure of interrupt request register 2 ............................................................... 2-17 fig. 2.2.13 structure of interrupt control register 1 ................................................................ 2-18 fig. 2.2.14 structure of interrupt control register 2 ................................................................ 2-18 fig. 2.2.15 timers connection and setting of division ratios ................................................. 2-20 fig. 2.2.16 relevant registers setting ....................................................................................... 2-21 fig. 2.2.17 control procedure ..................................................................................................... 2-22 fig. 2.2.18 peripheral circuit example ....................................................................................... 2-23 fig. 2.2.19 timers connection and setting of division ratios ................................................. 2-23 fig. 2.2.20 relevant registers setting ....................................................................................... 2-24 fig. 2.2.21 control procedure ..................................................................................................... 2-24 fig. 2.2.22 judgment method of valid/invalid of input pulses ............................................... 2-25 fig. 2.2.23 relevant registers setting ....................................................................................... 2-26 fig. 2.2.24 control procedure ..................................................................................................... 2-27 fig. 2.2.25 timers connection and setting of division ratios ................................................. 2-28 fig. 2.2.26 relevant registers setting ....................................................................................... 2-29 fig. 2.2.27 control procedure ..................................................................................................... 2-30 fig. 2.2.28 timers connection and table example of timer x/rtp setting values ............. 2-32 fig. 2.2.29 rtp output example ................................................................................................ 2-32 fig. 2.2.30 relevant registers setting ....................................................................................... 2-33 fig. 2.2.31 control procedure ..................................................................................................... 2-34 fig. 2.3.1 memory map of registers relevant to serial i/o .................................................... 2-35 fig. 2.3.2 structure of serial i/o1 automatic transfer data pointer ...................................... 2-36 fig. 2.3.3 structure of serial i/o1 control register 1 .............................................................. 2-37 fig. 2.3.4 structure of serial i/o1 control register 2 .............................................................. 2-38 fig. 2.3.5 structure of serial i/o1 register/transfer counter ................................................. 2-39 fig. 2.3.6 structure of serial i/o1 control register 3 .............................................................. 2-40 fig. 2.3.7 structure of baud rate generator ............................................................................. 2-41 fig. 2.3.8 structure of uart control register .......................................................................... 2-41 fig. 2.3.9 structure of serial i/o2 control register .................................................................. 2-42 fig. 2.3.10 structure of serial i/o2 status register ................................................................. 2-43 fig. 2.3.11 structure of serial i/o2 transmit/receive buffer register ..................................... 2-43 fig. 2.3.12 structure of interrupt source switch register ........................................................ 2-44 fig. 2.3.13 structure of interrupt request register 1 ............................................................... 2-44 fig. 2.3.14 structure of interrupt request register 2 ............................................................... 2-45 fig. 2.3.15 structure of interrupt control register 1 ................................................................ 2-46 fig. 2.3.16 structure of interrupt control register 2 ................................................................ 2-46 fig. 2.3.17 serial i/o1 connection examples (1) ..................................................................... 2-47 fig. 2.3.18 serial i/o1 connection examples (2) ..................................................................... 2-48 fig. 2.3.19 serial i/o1s modes ................................................................................................. 2-49 fig. 2.3.20 connection diagram ................................................................................................. 2-50 fig. 2.3.21 timing chart .............................................................................................................. 2-50
iv 38b5 group users manual list of figures fig. 2.3.22 registers setting relevant to transmission side ................................................... 2-51 fig. 2.3.23 setting of transmission data ................................................................................... 2-51 fig. 2.3.24 control procedure ..................................................................................................... 2-52 fig. 2.3.25 connection diagram ................................................................................................. 2-53 fig. 2.3.26 timing chart of serial data transmission/reception .............................................. 2-53 fig. 2.3.27 relevant registers setting ....................................................................................... 2-54 fig. 2.3.28 control procedure ..................................................................................................... 2-55 fig. 2.3.29 serial i/o2 connection examples (1) ..................................................................... 2-56 fig. 2.3.30 serial i/o2 connection examples (2) ..................................................................... 2-57 fig. 2.3.31 serial i/o2s modes ................................................................................................. 2-58 fig. 2.3.32 serial i/o2 transfer data format ............................................................................. 2-58 fig. 2.3.33 connection diagram ................................................................................................. 2-59 fig. 2.3.34 timing chart .............................................................................................................. 2-59 fig. 2.3.35 registers setting relevant to transmission side ................................................... 2-60 fig. 2.3.36 registers setting relevant to reception side ......................................................... 2-61 fig. 2.3.37 control procedure of transmission side ................................................................ 2-62 fig. 2.3.38 control procedure of reception side ...................................................................... 2-63 fig. 2.3.39 connection diagram ................................................................................................. 2-64 fig. 2.3.40 timing chart .............................................................................................................. 2-64 fig. 2.3.41 relevant registers setting ....................................................................................... 2-65 fig. 2.3.42 setting of transmission data ................................................................................... 2-65 fig. 2.3.43 control procedure ..................................................................................................... 2-66 fig. 2.3.44 connection diagram ................................................................................................. 2-67 fig. 2.3.45 timing chart .............................................................................................................. 2-68 fig. 2.3.46 relevant registers setting in master unit .............................................................. 2-68 fig. 2.3.47 relevant registers setting in slave unit ................................................................ 2-69 fig. 2.3.48 control procedure of master unit ........................................................................... 2-70 fig. 2.3.49 control procedure of slave unit ............................................................................. 2-71 fig. 2.3.50 connection diagram ................................................................................................. 2-72 fig. 2.3.51 timing chart .............................................................................................................. 2-72 fig. 2.3.52 registers setting relevant to transmission side ................................................... 2-74 fig. 2.3.53 registers setting relevant to reception side ......................................................... 2-75 fig. 2.3.54 control procedure of transmission side ................................................................ 2-76 fig. 2.3.55 control procedure of reception side ...................................................................... 2-77 fig. 2.3.56 sequence of setting serial i/o2 control register again ....................................... 2-81 fig. 2.4.1 memory assignment of fld controller relevant registers ..................................... 2-83 fig. 2.4.2 structure of p1fldram write disable register ...................................................... 2-84 fig. 2.4.3 structure of p3fldram write disable register ...................................................... 2-85 fig. 2.4.4 structure of fld mode register ............................................................................... 2-86 fig. 2.4.5 structure of tdisp time set register ......................................................................... 2-87 fig. 2.4.6 structure of toff1 time set register ......................................................................... 2-88 fig. 2.4.7 structure of toff2 time set register ......................................................................... 2-88 fig. 2.4.8 structure of fld data pointer/fld data pointer reload register ......................... 2-89 fig. 2.4.9 structure of port p0fld/port switch register .......................................................... 2-89 fig. 2.4.10 structure of port p2fld/port switch register ....................................................... 2-90 fig. 2.4.11 structure of port p8fld/port switch register ....................................................... 2-90 fig. 2.4.12 structure of port p8fld output control register .................................................. 2-91 fig. 2.4.13 structure of interrupt request register 2 ............................................................... 2-91 fig. 2.4.14 structure of interrupt control register 2 ................................................................ 2-92 fig. 2.4.15 connection diagram ................................................................................................. 2-93 fig. 2.4.16 timing chart of key-scan using fld automatic display mode and segments. 2-93
v 38b5 group users manual list of figures fig. 2.4.17 enlarged view of fld 0 (p2 0 ) to fld 7 (p2 7 ) tscan .............................................. 2-93 fig. 2.4.18 setting of relevant registers ................................................................................... 2-94 fig. 2.4.19 fld digit allocation example .................................................................................. 2-97 fig. 2.4.20 control procedure ..................................................................................................... 2-98 fig. 2.4.21 connection diagram ............................................................................................... 2-100 fig. 2.4.22 timing chart of key-scan using fld automatic display mode and digits ...... 2-101 fig. 2.4.23 setting of relevant registers ................................................................................. 2-102 fig. 2.4.24 fld digit allocation example ................................................................................ 2-105 fig. 2.4.25 control procedure ................................................................................................... 2-106 fig. 2.4.26 connection diagram ............................................................................................... 2-108 fig. 2.4.27 timing chart of fld display by software ........................................................... 2-108 fig. 2.4.28 enlarged view of p2 0 to p2 7 key-scan ................................................................ 2-108 fig. 2.4.29 setting of relevant registers ................................................................................. 2-109 fig. 2.4.30 fld digit allocation example ................................................................................ 2-110 fig. 2.4.31 control procedure ................................................................................................... 2-111 fig. 2.4.32 connection diagram ............................................................................................... 2-112 fig. 2.4.33 timing chart of 38b5 group and m35501fp ..................................................... 2-113 fig. 2.4.34 timing chart (enlarged view) of digit and segment output .............................. 2-113 fig. 2.4.35 setting of relevant registers ................................................................................. 2-114 fig. 2.4.36 fld digit allocation example ................................................................................ 2-117 fig. 2.4.37 control procedure ................................................................................................... 2-117 fig. 2.4.38 connection diagram ............................................................................................... 2-118 fig. 2.4.39 timing chart (at correct state) of 38b5 group and m35501fp ...................... 2-119 fig. 2.4.40 timing chart (at incorrect state) of 38b5 group and m35501fp ................... 2-119 fig. 2.4.41 setting of relevant registers ................................................................................. 2-120 fig. 2.4.42 control procedure ................................................................................................... 2-122 fig. 2.5.1 memory assignment of a-d converter relevant registers ................................... 2-125 fig. 2.5.2 structure of a-d control register ............................................................................ 2-125 fig. 2.5.3 structure of a-d conversion register (low-order) ................................................. 2-126 fig. 2.5.4 structure of a-d conversion register (high-order) ............................................... 2-126 fig. 2.5.5 structure of interrupt request register 2 ............................................................... 2-127 fig. 2.5.6 structure of interrupt control register 2 ................................................................ 2-128 fig. 2.5.7 connection diagram ................................................................................................. 2-129 fig. 2.5.8 setting of relevant registers ................................................................................... 2-129 fig. 2.5.9 control procedure ..................................................................................................... 2-130 fig. 2.6.1 memory assignment of pwm relevant registers .................................................. 2-132 fig. 2.6.2 structure of pwm register (high-order) ................................................................. 2-132 fig. 2.6.3 structure of pwm register (low-order) .................................................................. 2-133 fig. 2.6.4 structure of pwm control register ......................................................................... 2-133 fig. 2.6.5 connection diagram ................................................................................................. 2-134 fig. 2.6.6 setting of relevant registers ................................................................................... 2-134 fig. 2.6.7 control procedure ..................................................................................................... 2-135 fig. 2.6.8 pwm 0 output ............................................................................................................. 2-135 fig. 2.7.1 memory assignment of interrupt interval determination function relevant registers ............................................................................................................................... ....................... 2-136 fig. 2.7.2 structure of interrupt interval determination register ........................................... 2-136 fig. 2.7.3 structure of interrupt interval determination control register ............................. 2-137 fig. 2.7.4 structure of interrupt edge selection register ....................................................... 2-137 fig. 2.7.5 structure of interrupt request register 1 ............................................................... 2-138 fig. 2.7.6 structure of interrupt control register 1 ................................................................ 2-139 fig. 2.7.7 connection diagram ................................................................................................. 2-140
vi 38b5 group users manual list of figures fig. 2.7.8 function block diagram ........................................................................................... 2-140 fig. 2.7.9 timing chart of data determination ........................................................................ 2-140 fig. 2.7.10 setting of relevant registers ................................................................................. 2-141 fig. 2.7.11 control procedure ................................................................................................... 2-142 fig. 2.7.12 reception of remote-control data (timer 2 interrupt) ........................................ 2-143 fig. 2.8.1 memory assignment of watchdog timer relevant register ................................... 2-144 fig. 2.8.2 structure of watchdog timer control register ........................................................ 2-144 fig. 2.8.3 connection of watchdog timer and setting of division ratio ............................... 2-145 fig. 2.8.4 setting of relevant registers ................................................................................... 2-145 fig. 2.8.5 control procedure ..................................................................................................... 2-146 fig. 2.9.1 memory assignment of buzzer output circuit relevant register .......................... 2-147 fig. 2.9.2 structure of buzzer output control register ........................................................... 2-147 fig. 2.9.3 connection of buzzer output circuit and setting of division ratio ...................... 2-148 fig. 2.9.4 setting of relevant register ..................................................................................... 2-148 fig. 2.9.5 control procedure ..................................................................................................... 2-148 fig. 2.10.1 example of power-on reset circuit ....................................................................... 2-149 fig. 2.10.2 ram backup system example .............................................................................. 2-149 fig. 2.11.1 structure of cpu mode register .......................................................................... 2-151 fig. 2.11.2 connection diagram ............................................................................................... 2-152 fig. 2.11.3 status transition diagram during power failure .................................................. 2-152 fig. 2.11.4 setting of relevant registers ................................................................................. 2-153 fig. 2.11.5 control procedure ................................................................................................... 2-154 fig. 2.11.6 structure of clock counter ..................................................................................... 2-155 fig. 2.11.7 initial setting of relevant registers ....................................................................... 2-156 fig. 2.11.8 setting of relevant registers after detecting power failure ............................... 2-157 fig. 2.11.9 control procedure ................................................................................................... 2-158 chapter 3 appendix fig. 3.1.1 circuit for measuring output switching characteristics ............................................ 3-6 fig. 3.1.2 timing diagram ............................................................................................................. 3-7 fig. 3.2.1 power source current standard characteristics ........................................................ 3-8 fig. 3.2.2 power source current standard characteristics (in wait mode) ............................. 3-8 fig. 3.2.3 high-breakdown p-channel open-drain output port characteristics (25 c) ......... 3-9 fig. 3.2.4 high-breakdown p-channel open-drain output port characteristics (90 c) ......... 3-9 fig. 3.2.5 cmos output port p-channel side characteristics (25 c) .................................. 3-10 fig. 3.2.6 cmos output port p-channel side characteristics (90 c) .................................. 3-10 fig. 3.2.7 cmos output port n-channel side characteristics (25 c) .................................. 3-11 fig. 3.2.8 cmos output port n-channel side characteristics (90 c) .................................. 3-11 fig. 3.2.9 n-channel open-drain output port characteristics (25 c) .................................... 3-12 fig. 3.2.10 n-channel open-drain output port characteristics (90 c) .................................. 3-12 fig. 3.2.11 a-d conversion standard characteristics ............................................................... 3-13 fig. 3.3.1 sequence of switch detection edge ......................................................................... 3-14 fig. 3.3.2 sequence of check of interrupt request bit ............................................................ 3-14 fig. 3.3.3 structure of interrupt control register 2 .................................................................. 3-15 fig. 3.3.4 sequence of setting serial i/o2 control register again ......................................... 3-18 fig. 3.3.5 pwm output ................................................................................................................ 3-19 fig. 3.3.6 initialization of processor status register ................................................................ 3-22 fig. 3.3.7 sequence of plp instruction execution .................................................................. 3-22 fig. 3.3.8 stack memory contents after php instruction execution ..................................... 3-22
vii 38b5 group users manual list of figures fig. 3.3.9 status flag at decimal calculations .......................................................................... 3-23 fig. 3.3.10 programming and testing of one time prom version ...................................... 3-23 fig. 3.4.1 selection of packages ............................................................................................... 3-26 fig. 3.4.2 wiring for the reset pin ......................................................................................... 3-26 fig. 3.4.3 wiring for clock i/o pins ........................................................................................... 3-27 fig. 3.4.4 wiring for the v pp pin of the one time prom and the eprom version ......... 3-28 fig. 3.4.5 bypass capacitor across the v ss line and the v cc line ........................................ 3-28 fig. 3.4.6 analog signal line and a resistor and a capacitor ................................................ 3-29 fig. 3.4.7 wiring for a large current signal line ...................................................................... 3-29 fig. 3.4.8 wiring of signal lines where potential levels change frequently ......................... 3-30 fig. 3.4.9 v ss pattern on the underside of an oscillator ........................................................ 3-30 fig. 3.4.10 setup for i/o ports ................................................................................................... 3-31 fig. 3.4.11 watchdog timer by software ................................................................................... 3-32 fig. 3.5.1 structure of port pi .................................................................................................... 3-33 fig. 3.5.2 structure of port pi direction register ...................................................................... 3-33 fig. 3.5.3 structure of port p6 ................................................................................................... 3-34 fig. 3.5.4 structure of port p6 direction register .................................................................... 3-34 fig. 3.5.5 structure of port p9 ................................................................................................... 3-35 fig. 3.5.6 structure of port p9 direction register .................................................................... 3-35 fig. 3.5.7 structure of pwm register (high-order) ................................................................... 3-36 fig. 3.5.8 structure of pwm register (low-order) .................................................................... 3-36 fig. 3.5.9 structure of baud rate generator ............................................................................. 3-37 fig. 3.5.10 structure of uart control register ........................................................................ 3-37 fig. 3.5.11 structure of serial i/o1 automatic transfer data pointer ..................................... 3-38 fig. 3.5.12 structure of serial i/o1 control register 1 ............................................................ 3-38 fig. 3.5.13 structure of serial i/o1 control register 2 ............................................................ 3-39 fig. 3.5.14 structure of serial i/o1 register/transfer counter ................................................ 3-40 fig. 3.5.15 structure of serial i/o1 control register 3 ............................................................ 3-41 fig. 3.5.16 structure of serial i/o2 control register ................................................................ 3-42 fig. 3.5.17 structure of serial i/o2 status register ................................................................. 3-43 fig. 3.5.18 structure of serial i/o2 transmit/receive buffer register ..................................... 3-43 fig. 3.5.19 structure of timer i ................................................................................................... 3-44 fig. 3.5.20 structure of timer 2 ................................................................................................. 3-44 fig. 3.5.21 structure of pwm control register ......................................................................... 3-44 fig. 3.5.22 structure of timer 6 pwm register ........................................................................ 3-45 fig. 3.5.23 structure of timer 12 mode register ...................................................................... 3-45 fig. 3.5.24 structure of timer 34 mode register ...................................................................... 3-46 fig. 3.5.25 structure of timer 56 mode register ...................................................................... 3-46 fig. 3.5.26 structure of watchdog timer control register ........................................................ 3-47 fig. 3.5.27 structure of timer x (low-order, high-order) ......................................................... 3-47 fig. 3.5.28 structure of timer x mode register 1 .................................................................... 3-48 fig. 3.5.29 structure of timer x mode register 2 .................................................................... 3-49 fig. 3.5.30 structure of interrupt interval determination register .......................................... 3-49 fig. 3.5.31 structure of interrupt interval determination control register ............................. 3-50 fig. 3.5.32 structure of a-d control register ............................................................................ 3-50 fig. 3.5.33 structure of a-d conversion register (low-order) ................................................. 3-51 fig. 3.5.34 structure of a-d conversion register (high-order) ............................................... 3-51 fig. 3.5.35 structure of interrupt source switch register ........................................................ 3-52 fig. 3.5.36 structure of interrupt edge selection register ...................................................... 3-52 fig. 3.5.37 structure of cpu mode register ............................................................................ 3-53 fig. 3.5.38 structure of interrupt request register 1 ............................................................... 3-54
viii 38b5 group users manual list of figures fig. 3.5.39 structure of interrupt request register 2 ............................................................... 3-55 fig. 3.5.40 structure of interrupt control register 1 ................................................................ 3-56 fig. 3.5.41 structure of interrupt control register 2 ................................................................ 3-57 fig. 3.5.42 structure of pull-up control register 1 ................................................................... 3-58 fig. 3.5.43 structure of pull-up control register 2 ................................................................... 3-58 fig. 3.5.44 structure of p1fldram write disable register .................................................... 3-59 fig. 3.5.45 structure of p3fldram write disable register .................................................... 3-60 fig. 3.5.46 structure of fldc mode register .......................................................................... 3-61 fig. 3.5.47 structure of tdisp time set register ...................................................................... 3-62 fig. 3.5.48 structure of toff1 time set register ....................................................................... 3-63 fig. 3.5.49 structure of toff2 time set register ....................................................................... 3-63 fig. 3.5.50 structure of fld data pointer/fld data pointer reload register ....................... 3-64 fig. 3.5.51 structure of port p0fld/port switch register ....................................................... 3-64 fig. 3.5.52 structure of port p2fld/port switch register ....................................................... 3-65 fig. 3.5.53 structure of port p8fld/port switch register ....................................................... 3-65 fig. 3.5.54 structure of port p8fld output control register .................................................. 3-66 fig. 3.5.55 structure of buzzer output control register ........................................................... 3-66 fig. 3.12.1 pin configuration of m35501fp .............................................................................. 3-91 fig. 3.12.2 functional block diagram ........................................................................................ 3-92 fig. 3.12.3 port block diagram ................................................................................................... 3-93 fig. 3.12.4 digit setting ............................................................................................................... 3-94 fig. 3.12.5 16-digit mode output waveform .............................................................................. 3-95 fig. 3.12.6 optional digit mode output waveform ................................................................... 3-95 fig. 3.12.7 cascade mode connection example: 17 digits or more selected ..................... 3-96 fig. 3.12.8 cascade mode output waveform ........................................................................... 3-96 fig. 3.12.9 connection example with 38b5 group microcomputer (1 to 16 digits) ........... 3-97 fig. 3.12.10 connection example with 38b5 group microccomputer (17 to 32 digits) ..... 3-97 fig. 3.12.11 digit output waveform when reset signal is input ............................................. 3-98 fig. 3.12.12 power-on reset circuit ........................................................................................... 3-99 fig. 3.12.13 timing diagram ..................................................................................................... 3-102
i 38b5 group users manual list of tables list of tables chapter 1 hardware table 1 pin description (1) ........................................................................................................... 1-4 table 2 pin description (2) ........................................................................................................... 1-5 table 3 list of supported products ............................................................................................. 1-7 table 4 push and pop instructions of accumulator or processor status register ................. 1-9 table 5 set and clear instructions of each bit of processor status register ....................... 1-10 table 6 list of i/o port functions (1) ........................................................................................ 1-15 table 7 list of i/o port functions (2) ........................................................................................ 1-16 table 8 interrupt vector addresses and priority ...................................................................... 1-21 table 9 pins in fld automatic display mode .......................................................................... 1-42 table 10 relationship between low-order 6-bit data and setting period of add bit ......... 1-54 table 11 special programming adapter .................................................................................... 1-66 table 12 mask option type of pull-down resistor .................................................................... 1-67 table 13 interrupt sources, vector addresses and interrupt priority ..................................... 1-69 table 14 relative formula for a refernece voltage v ref of a-d converter and v ref ..................... 1-71 table 15 change of a-d conversion register during a-d conversion .................................. 1-71 chapter 2 application table 2.1.1 termination of unused pins ..................................................................................... 2-6 table 2.3.1 setting examples of baud rate generator values and transfer bit rate values ............................................................................................................................... ......................... 2-73 table 2.4.1 fld automatic display ram map ......................................................................... 2-96 table 2.4.2 fld automatic display ram map example ......................................................... 2-97 table 2.4.3 fld automatic display ram map ....................................................................... 2-104 table 2.4.4 fld automatic display ram map example ....................................................... 2-105 table 2.4.5 fld automatic display ram map example ....................................................... 2-110 table 2.4.6 fld automatic display ram map ....................................................................... 2-116 chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions (1) ................................................................ 3-3 table 3.1.3 recommended operating conditions (2) ................................................................ 3-4 table 3.1.4 electrical characteristics (1) ..................................................................................... 3-4 table 3.1.5 electrical characteristics (2) ..................................................................................... 3-5 table 3.1.6 a-d converter characteristics .................................................................................. 3-5 table 3.1.7 timing requirements ................................................................................................. 3-6 table 3.1.8 switching characteristics .......................................................................................... 3-6 table 3.3.1 programming adapter ............................................................................................. 3-24 table 3.3.2 prom programmer address setting ..................................................................... 3-24 table 3.12.1 pin description ....................................................................................................... 3-92 table 3.12.2 absolute maximum ratings ................................................................................. 3-100 table 3.12.3 recommended operating conditions ................................................................. 3-100 table 3.12.4 recommended operating conditions ................................................................. 3-100 table 3.12.5 electrical characteristics ..................................................................................... 3-101 table 3.12.6 timing requirements ........................................................................................... 3-102
chapter 1 chapter 1 hardware description features application pin configuration functional block pin description part numbering group expansion functional description notes on programming notes on use data required for mask orders data required for rom writing orders rom programming method mask option of pull-down resistor functional description supplement
38b5 group user?s manual 1-2 hardware description/features/application/pin configuration description the 38b5 group is the 8-bit microcomputer based on the 740 family core technology. the 38b5 group has six 8-bit timers, a 16-bit timer, a fluorescent dis- play automatic display circuit, 12-channel 10-bit a-d converter, a se- rial i/o with automatic transfer function, which are available for con- trolling musical instruments and household appliances. the 38b5 group has variations of internal memory size and packag- ing. for details, refer to the section on part numbering. for details on availability of microcomputers in the 38b5 group, refer to the section on group expansion. built-in pull-down resistors connected to high-breakdown voltage ports are available by specifying with the mask option in some products. for the details, refer to the section on the mask option of pull-down resis- tor. features basic machine-language instructions ....................................... 71 the minimum instruction execution time .......................... 0.48 m s (at 4.19 mhz oscillation frequency) memory size rom ............................................. 24k to 60k bytes ram .......................................... 1024 to 2048 bytes programmable input/output ports ............................................. 55 high-breakdown-voltage output ports ...................................... 36 software pull-up resistors ....... (ports p5, p6 1 to p6 5 , p7, p8 4 to p8 7 , p9) interrupts .................................................. 21 sources, 16 vectors timers ........................................................... 8-bit 5 6, 16-bit 5 1 serial i/o1 (clock-synchronized) ................................... 8-bit 5 1 ...................... (max. 256-byte automatic transfer function) fig. 1 pin configuration of m38b5xmxh-xxxxfp package type : 80p6n-a 80-pin plastic-molded qfp pin configuration (top view) serial i/o2 (uart or clock-synchronized) .................... 8-bit 5 1 pwm ............................................................................ 14-bit 5 1 8-bit 5 1 (also functions as timer 6) a-d converter .............................................. 10-bit 5 12 channels fluorescent display function ......................... total 40 control pins interrupt interval determination function ..................................... 1 watchdog timer ............................................................ 20-bit 5 1 buzzer output ............................................................................. 1 2 clock generating circuit main clock (x in ex out ) .......................... internal feedback resistor sub-clock (x cin ex cout ) .......... without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode ................................................... 4.0 to 5.5 v (at 4.19 mhz oscillation frequency and high-speed selected) in middle-speed mode ................................................ 2.7 to 5.5 v (at 4.19 mhz oscillation frequency and middle-speed selected) in low-speed mode ..................................................... 2.7 to 5.5 v (at 32 khz oscillation frequency) power dissipation in high-speed mode .......................................................... 35 mw (at 4.19 mhz oscillation frequency) in low-speed mode ............................................................. 60 m w (at 32 khz oscillation frequency, at 3 v power source voltage) operating temperature range ................................... e20 to 85 c application musical instruments, vcr, household appliances, etc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p2 0 /b uz02 /fld 0 p2 1 /fld 1 p2 2 /fld 2 p2 3 /fld 3 p2 4 /fld 4 p2 5 /fld 5 p2 6 /fld 6 p2 7 /fld 7 p0 0 /fld 8 p0 3 /fld 11 p0 4 /fld 12 p0 5 /fld 13 p0 6 /fld 14 p0 7 /fld 15 p1 1 /fld 17 p1 2 /fld 18 p1 3 /fld 19 p1 4 /fld 20 p1 5 /fld 21 p1 6 /fld 22 p1 7 /fld 23 p7 1 /an 1 p7 0 /an 0 p6 5 /s stb1 /an 11 p6 4 /int 4 /s busy1 /an 10 m38b5xmxh-xxxxfp p6 0 /cntr 1 p6 3 /an 9 p6 2 /s rdy1 /an 8 reset p9 1 /x cout p9 0 /x cin p4 4 /pwm 1 p4 3 /b uz01 p4 2 /int 3 p4 1 /int 1 p4 0 /int 0 v ee p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 v ref av ss p5 0 /s in1 p5 1 /s out1 p5 2 /s clk11 p5 3 /s clk12 p5 4 /rxd p5 5 /txd p5 6 /s clk21 p5 7 /s rdy2/ s clk22 p8 7 /pwm 0 /fld 39 p8 6 /rtp 1 /fld 38 p8 3 /fld 35 p8 2 /fld 34 p8 1 /fld 33 p8 0 /fld 32 p3 7 /fld 31 p3 6 /fld 30 p3 5 /fld 29 p3 4 /fld 28 p3 3 /fld 27 p3 2 /fld 26 p3 1 /fld 25 p3 0 /fld 24 p8 5 /rtp 0 /fld 37 p6 1 /cntr 0 /cntr 2 p4 5 /t 1out x in x out vcc p4 6 /t 3out vss p1 0 /fld 16 p0 1 /fld 9 p0 2 /fld 10 p4 7 /int 2 p8 4 /fld 36 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 note: in the mask option type p, int 3 and cntr 1 cannot be used. (note) (note)
38b5 group users manual 1-3 hardware functional block fig. 2 functional block diagram functional block diagram (package : 80p6n-a) functional block port p0(8) 8 port p1(8) 8 port p2(8) 8 port p3(8) 8 port p4(8) 7 port p5(8) 8 port p6(6) 6 port p7(8) 8 port p8(8) 8 port p9(2) 2 system clock generation x in -x out (main-clock) x cin -x cout (sub-clock) timers timer x(16-bit) timer 1(8-bit) timer 2(8-bit) timer 3(8-bit) timer 4(8-bit) timer 5(8-bit) timer 6(8-bit) a-d converter (10-bit 5 12 channel) cpu core watchdog timer rom ram build-in peripheral functions memory i/o ports pwm0(14-bit) pwm1(8-bit) serial i/o serial i/o1(clock-synchronized) (256 byte automatic transfer) serial i/o2 (clock-synchronized or uart) fld display function 40 control pins (36 high-breakdown voltage ports) interrupt interval determination function 1 buzzer output
38b5 group user?s manual 1-4 hardware pin description pin description table 1 pin description (1) pin name function v cc , v ss power source apply voltage of 4.0e5.5 v to v cc , and 0 v to v ss . v ee pull-down apply voltage supplied to pull-down resistors of ports p0, p1, and p3. power source v ref reference reference voltage input pin for a-d converter. voltage av ss analog power analog power source input pin for a-d converter. source connect to v ss . ______ reset reset input reset input pin for active l. x in clock input input and output pins for the main clock generating circuit. feedback resistor is built in between x in pin and x out pin. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. the clock is used as the oscillating source of system clock. p0 0 /fld 8 e i/o port p0 8-bit i/o port. fld automatic display p0 7 /fld 15 i/o direction register allows each pin to be individually programmed as either pins input or output. at reset, this port is set to input mode. a pull-down resistor is built in between port p0 and the v ee pin. cmos compatible input level. high-breakdown-voltage p-channel open-drain output structure. at reset, this port is set to v ee level. p1 0 /fld 16 e output port p1 8-bit output port. fld automatic display p1 7 /fld 23 a pull-down resistor is built in between port p1 and the v ee pin. pins high-breakdown-voltage p-channel open-drain output structure. at reset, this port is set to v ee level. p2 0 /b uz02 / i/o port p2 8-bit i/o port with the same function as port p0. fld automatic display fld 0 e low-voltage input level. pins p2 7 /fld 7 high-breakdown-voltage p-channel open-drain output structure. buzzer output pin (p2 0 ) p3 0 /fld 24 e output port p3 8-bit output port. fld automatic display p3 7 /fld 31 a pull-down resistor is built in between port p3 and the v ee pin. pins high-breakdown-voltage p-channel open-drain output structure. at reset, this port is set to v ee level. p4 0 /int 0 , i/o port p4 7-bit i/o port with the same function as port p0. interrupt input pins p4 1 /int 1 , cmos compatible input level in the mask option type p, p4 2 /int 3 n-channel open-drain output structure. int 3 cannot be used. p4 3 /b uz01 buzzer output pin p4 4 /pwm 1 pwm output pin (timer output pin) p4 5 /t 1out , timer output pin p4 6 /t 3out p4 7 /int 2 input port p4 1-bit input port. interrupt input pin cmos compatible input level. function except a port function x out clock output
38b5 group users manual 1-5 hardware pin description table 2 pin description (2) function except a port function pin name function p5 0 /s in1 , i/o port p5 ? 8-bit cmos i/o port with the same function as port p0. ? serial i/o1 function pins p5 1 /s out1 , ? cmos compatible input level. p5 2 /s clk11 , ? cmos 3-state output structure. p5 3 /s clk12 p5 4 /r x d, ? serial i/o2 function pins p5 5 /t x d, p5 6 /s clk21 , p5 7 /s rdy2 / s clk22 p6 0 /cntr 1 i/o port p6 ? 1-bit i/o port with the same function as port p0. ? timer input pin ? cmos compatible input level. in the mask option type p, ? n-channel open-drain output structure. cntr 1 cannot be used. p6 1 /cntr 0 / ? 5-bit cmos i/o port with the same function as port p0. ? timer i/o pin cntr 2 ? cmos compatible input level. p6 2 /s rdy1 / ? cmos 3-state output structure. ? serial i/o1 function pin an 8 ? a-d conversion input pin p6 3 /an 9 ? a-d conversion input pin ? dimmer signal output pin p6 4 /int 4 / ? serial i/o1 function pin s busy1 /an 10 , ? a-d conversion input pin p6 5 /s stb1 / ? interrupt input pin (p6 4 ) an 11 p7 0 /an 0 C i/o port p7 ? 8-bit cmos i/o port with the same function as port p0. ? a-d conversion input pin p7 7 /an 7 ? cmos compatible input level. ? cmos 3-state output structure. p8 0 /fld 32 C i/o port p8 ? 4-bit i/o port with the same function as port p0. ? fld automatic display pins p8 3 /fld 35 ? low-voltage input level. ? high-breakdown-voltage p-channel open-drain output structure. p8 4 /fld 36 ? 4-bit cmos i/o port with the same function as port p0. p8 5 /rtp 0 / ? low-voltage input level. ? fld automatic display pins fld 37, ? cmos 3-state output structure ? real time port output p8 6 /rtp 1 / fld 38 p8 7 /pwm 0 / ? fld automatic display pins fld 39 ? 14-bit pwm output p9 0 /x cin , i/o port p9 ? 2-bit cmos i/o port with the same function as port p0. ? i/o pins for sub-clock generating p9 1 /x cout ? cmos compatible input level. circuit (connect a ceramic resona- ? cmos 3-state output structure. tor or a quarts-crystal oscillator)
38b5 group users manual 1-6 hardware part numbering part numbering fig. 3 part numbering m38b5 7 m c h - xxxx fp product package type fp : 80p6n-a package fs : 80d0 package rom number omitted in one time prom version shipped in blank and eprom version. 3 digits for m38b57m6-xxxfp and one time prom version. rom/prom size 1 2 3 4 5 6 7 8 9 a b c d e f : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used for users. memory type m e : mask rom version : eprom or one time prom version ram size 0 1 2 3 4 5 6 7 8 9 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes high-breakdown voltage pull-down option regarding option contents, refer to section mask option of pull-down resistor? for the m38b57m6-xxxfp, one time prom version, and eprom version, there is not the option specification.
38b5 group user?s manual 1-7 hardware 60k 56k 52k 48k 44k 36k 32k 28k 24k 20k 16k 12k 8k 4k 40k rom size (bytes) 256 512 768 1,024 1,536 2,048 ram size (bytes) m38b59ef m38b57m6 m38b57mch mass product mass product mass product m38b59mfh new product group expansion group expansion mitsubishi plans to expand the 38b5 group as follows: memory type support for mask rom, one time prom and eprom versions. memory size rom/prom size .................................................. 24k to 60k bytes ram size ............................................................ 1024 to 2048 bytes package 80p6n-a ..................................... 0.8 mm-pitch plastic molded qfp 80d0 ........................ 0.8 mm-pitch ceramic lcc (eprom version) fig. 4 memory expansion plan currently supported products are listed below. table 3 list of supported products note : products under development or planning : the development schedule and specifications may be revised without notice. as of nov. 1998 product m38b57m6-xxxfp m38b57mch-xxxxfp m38b59mfh-xxxxfp m38b59ef-xxxfp m38b59effp m38b59effs (p) rom size (bytes) rom size for user ( ) 24576 (24446) 49152 (49022) 61440 (61310) 61440 (61310) 61440 (61310) 61440 (61310) ram size (bytes) 1024 1024 2048 2048 2048 2048 package 80p6n-a 80p6n-a 80p6n-a 80p6n-a 80p6n-a 80d0 remarks mask rom version corresponded to mask option mask rom version mask rom version corresponded to mask option one time prom version one time prom version (blank) eprom version
38b5 group users manual 1-8 hardware functional description functional description central processing unit (cpu) the 38b5 group uses the standard 740 family instruction set. re- fer to the table of 740 series addressing modes and machine instructions or the 740 series software manual for details on the instruction set. machine-resident 740 series instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1, the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 6. store registers other than those described in figure 6 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
38b5 group users manual 1-9 hardware functional description table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
38b5 group users manual 1-10 hardware functional description [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. ?bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. ?bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0, and cleared if the result is anything other than 0. ?bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1. ?bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0; decimal arithmetic is executed when it is 1. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. ?bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1. ?bit 5: index x mode flag (t) when the t flag is 0, arithmetic operations are performed between accumulator and memory. when the t flag is 1, direct arithmetic operations and direct data transfers are enabled between memory locations. ?bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. ?bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag z flag i flag d flag b flag t flag v flag n flag sec clc _ _ sei cli sed cld _ _ set clt clv _ _ _
38b5 group users manual 1-11 hardware functional description cpu mode register ( cpum: address 003b 16 ) b7 b0 stack page selection bit 0: page 0 1: page 1 x cout drivability selection bit 0: low drive 1: high drive processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : not available 1 1 : port x c switch bit 0: i/o port function 1: x cin ? cout oscillating function main clock (x in ? out ) stop bit 0: oscillating 1: stopped main clock division ratio selection bit 0: f(x in ) (high-speed mode) 1: f(x in )/4 (middle-speed mode) internal system clock selection bit 0: x in -x out selection (middle-/high-speed mode) 1: x cin -x cout selection (low-speed mode) [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit etc. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register
38b5 group users manual 1-12 hardware functional description memory special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing, and the other areas are user areas for storing pro- grams. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 1536 2048 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom 0ef0 16 0f00 16 0eff 16 0fff 16 reserved area sfr area 1 not used (note) interrupt vector area rom area reserved rom area (common rom area,128 byte) zero page special page ram area ram size (byte) address xxxx 16 rom size (byte) address yyyy 16 reserved rom area address zzzz 16 sfr area 2 ram area for serial i/o automatic transfer ram area for fld automatic display note : when 1024 bytes or more are used as ram area, this area can be used.
38b5 group users manual 1-13 hardware functional description fig. 9 memory map of special function register (sfr) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 serial i/o2 transmit/receive buffer register (tb/rb) port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) pwm register (high-order) (pwmh) pwm register (low-order) (pwm l) baud rate generator (brg) uart control register (uartcon) serial i/o1 automatic transfer data pointer (sio1dp) serial i/o1 control register 1 (sio1con1) serial i/o1 control register 2 (sio1con2) serial i/o1 register/transfer counter (sio1) serial i/o1 control register 3 (sio1con3) serial i/o2 control register (sio2con) serial i/o2 status register (sio2sts) port p9 (p9) port p9 direction register (p9d) 0ef0 16 0ef1 16 0ef2 16 0ef3 16 0ef4 16 0ef5 16 0ef6 16 0ef7 16 toff2 time set register (toff2) pull-up control register 1 (pull1) pull-up control register 2 (pull2) p1fldram write disable register (p1fldram) p3fldram write disable register (p3fldram) fldc mode register (fldm) tdisp time set register (tdisp) toff1 time set register (toff1) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer x mode register 1 (txm1) interrupt control register 2(icon2) timer 1 (t1) timer 2 (t2) timer 3 (t3) timer 4 (t4) timer 5 (t5) timer 6 (t6) pwm control register (pwmcon) timer 6 pwm register (t6pwm) timer 12 mode register (t12m) timer 34 mode register (t34m) timer 56 mode register (t56m) watchdog timer control register (wdtcon) timer x (low-order) (txl) timer x (high-order) (txh) timer x mode register 2 (txm2) interrupt interval determination register (iid) interrupt interval determination control register (iidcon) a-d control register (adcon) a-d conversion register (low-order) (adl) a-d conversion register (high-order) (adh) interrupt source switch register (ifr) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) 0ef8 16 0ef9 16 0efa 16 0efb 16 0efc 16 0efd 16 0efe 16 0eff 16 fld data pointer (flddp) port p0fld/port switch register (p0fpr) port p2fld/port switch register (p2fpr) port p8fld/port switch register (p8fpr) port p8fld output control register (p8fldcon) buzzer output control register (buzcon)
38b5 group users manual 1-14 hardware 0: no pull-up 1: pull-up pull-up control register 2 (pull2 : address 0ef1 16 ) p7 0 , p7 1 pull-up control bit p7 2 , p7 3 pull-up control bit p7 4 , p7 5 pull-up control bit p7 6 , p7 7 pull-up control bit p8 4 , p8 5 pull-up control bit p8 6 , p8 7 pull-up control bit p9 0 , p9 1 pull-up control bit not used (returns ??when read) b7 b0 0: no pull-up 1: pull-up pull-up control register 1 (pull1 : address 0ef0 16 ) p5 0 , p5 1 pull-up control bit p5 2 , p5 3 pull-up control bit p5 4 , p5 5 pull-up control bit p5 6 , p5 7 pull-up control bit p6 1 pull-up control bit p6 2 , p6 3 pull-up control bit p6 4 , p6 5 pull-up control bit not used (returns ??when read) b7 b0 functional description i/o ports [direction registers] pid the 38b5 group has 55 programmable i/o pins arranged in eight individual i/o ports (p0, p2, p4 0 Cp4 6 , and p5Cp9). the i/o ports have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin becomes an input pin. when 1 is written to that pin, that pin becomes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input (the bit corresponding to that pin must be set to 0) are floating and the value of that pin can be read. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. [high-breakdown-voltage output ports] the 38b5 group has 5 ports with high-breakdown-voltage pins (ports p0Cp3 and p8 0 Cp8 3 ). the high-breakdown-voltage ports have p- channel open-drain output with vcc- 45 v of breakdown voltage. each pin in ports p0, p1, and p3 has an internal pull-down resistor con- nected to v ee . at reset, the p-channel output transistor of each port latch is turned off, so that it goes to v ee level (l) by the pull-down resistor. writing 1 (weak drivability) to bit 7 of the fldc mode register (ad- dress 0ef4 16 ) shows the rising transition of the output transistors for reducing transient noise. at reset, bit 7 of the fldc mode register is set to 0 (strong drivability). [pull-up control register] pull ports p5, p6 1 Cp6 5 , p7, p8 4 Cp8 7 and p9 have built-in programmable pull-up resistors. the pull-up resistors are valid only in the case that the each control bit is set to 1 and the corresponding port direction registers are set to input mode. fig. 10 structure of pull-up control registers (pull1 and pull2)
38b5 group users manual 1-15 hardware functional description table 6 list of i/o port functions (1) pin name input/output i/o format non-port function related sfrs ref.no. p0 0 /fld 8 C port p0 input/output, cmos compatible input level fld automatic display function fldc mode register (1) p0 7 /fld 15 individual bits high-breakdown voltage p- port p0fld/port switch register channel open-drain output with pull-down resistor p1 0 /fld 16 C port p1 output high-breakdown voltage p- fldc mode register (2) p1 7 /fld 23 channel open-drain output with pull-down resistor p2 0 /b uz02 / port p2 input/output, low-voltage input level buzzer output (p2 0 ) fldc mode register (3) fld 0 individual bits high-breakdown voltage p- fld automatic display function port p2fld/port switch register p2 1 /fld 1 C channel open-drain output fld automatic display function buzzer output control register (1) p2 7 /fld 7 p3 0 /fld 24 C port p3 output high-breakdown voltage p- fldc mode register (2) p3 7 /fld 31 channel open-drain output with pull-down resistor p4 0 /int 0 , port p4 input/output, cmos compatible input level external interrupt input interrupt edge selection register (5-1) p4 1 /int 1 , individual bits n-channel open-drain output in the mask option type p, int 3 (5-2) p4 2 /int 3 cannot be used. p4 3 /b uz01 buzzer output buzzer output control register (4) p4 4 /pwm 1 pwm output timer 56 mode register (6) p4 5 /t 1out timer output timer 12 mode register (7) p4 6 /t 3out timer output timer 34 mode register (7) p4 7 /int 2 input cmos compatible input level external interrput input i nterrupt edge selection register (8) interrupt interval determination control register p5 0 /s in1 port p5 input/output, cmos compatible input level serial i/o1 function i/o serial i/o1 control register 1, 2 (9) p5 1 /s out1 , individual bits cmos 3-state output (10) p5 2 /s clk11 , p5 3 /s clk12 p5 4 /r x d, serial i/o2 function i/o serial i/o2 control register (9) p5 5 /t x d, uart control register (10) p5 6 /s clk21 p5 7 /s rdy2 / (11) s clk22 p6 0 /cntr 1 port p6 cmos compatible input level external count input interrupt edge selection register (5-1) n-channel open-drain output in the mask option type p, (5-2) p6 1 /cntr 0 / cmos compatible input level cntr 1 cannot be used. (12) cntr 2 cmos 3-state output p6 2 /s rdy1 / serial i/o1 function i/o serial i/o1 control register 1, 2 (13) an 8 a-d conversion input a-d control register p6 3 /an 9 a-d conversion input a-d control register (14) dimmer signal output p8fld output control bit p6 4 /int 4 / serial i/o1 function i/o serial i/o1 control register 1, 2 (15) s busy1 / an 10 a-d conversion input a-d control register external interrupt input interrupt edge selection register p6 5 /s stb1 / serial i/o1 function i/o serial i/o1 control register 1, 2 (16) an 11 a-d conversion input a-d control register p7 0 /an 0 C port p7 a-d conversion input a-d control register (14) p7 7 /an 7
38b5 group users manual 1-16 hardware functional description table 7 list of i/o port functions (2) pin name input/output i/o format non-port function related sfrs ref.no. p8 0 /fld 32 C port p8 input/output, low-voltage input level fld automatic display function fldc mode register (1) p8 3 /fld 35 individual bits high-breakdown voltage p- port p8fld/port switch register channel open-drain output p8 4 /fld 36 low-voltage input level (17) p8 5 /rtp 0 / cmos 3-state output fld automatic display function fldc mode register (18) fld 37 , real time port output port p8fld/port switch register p8 6 /rtp 1 / timer x mode register 2 fld 38 p8 7 /pwm 0 / fld automatic display function fldc mode register (19) fld 39 pwm output port p8fld/port switch register pwm control register p9 0 /x cin port p9 cmos compatible input level sub-clock generating circuit i/o cpu mode register (20) p9 1 /x cout cmos 3-state output (21) notes 1 : how to use double-function ports as function i/o ports, refer to the applicable sections. 2 : make sure that the input level at each pin is either 0 v or vcc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from vcc to vss through the input-stage gate.
38b5 group user?s manual 1-17 hardware functional description fig. 11 port block diagram (1) (2) ports p1, p3 (3) port p2 0 (4) port p4 3 (6) port p4 4 (7) ports p4 5 , p4 6 * high-breakdown-voltage p-channel transistor notes 1: the dimmer signal sets the toff timing. 2: a pull-down resistor is not built in to ports p2 and p8. 3: in the mask option type p, the hysteresis circuit of part is not built-in. v ee * timer 1 output bit timer 3 output bit timer 1 output timer 3 output dimmer signal (note 1) * read buzzer control signal buzzer signal output timer 6 output selection bit timer 6 output int 0 , int 1 , int 3 interrupt input cntr 1 input timer 4 external clock input (1) ports p0, p2 1 ?2 7 , p8 0 ?8 3 data bus local data bus port latch dimmer signal (note 1) * fld/port switch register direction register read v ee (note 2) v ee fld/port switch register port latch direction register data bus local data bus (note 2) data bus local data bus port latch dimmer signal (note 1) (5-1) ports p4 0 ?4 2 , p6 0 port latch direction register data bus buzzer control signal buzzer signal output port latch direction register data bus port latch direction register data bus port latch direction register data bus (note 3) (5-2) ports p4 2 , p6 0 (in mask option type p) port latch direction register data bus
38b5 group user?s manual 1-18 hardware functional description fig. 12 port block diagram (2) serial ready output (9) ports p5 0 , p5 4 (13) port p6 2 (12) port p6 1 serial i/o input pull-up control (10) ports p5 1 ?5 3 , p5 5 , p5 6 serial clock input serial i/o2 mode selection bit output off control signal t x d, s out or s clk p5 2 ,p5 3 ,p5 6 p-channel output disable signal (p5 1 ,p5 5 ) timer x output timer x operating mode bit cntr 0 ,cntr 2 input timer 2, timer x external clock input (11) port p5 7 s rdy2 output enable bit serial clock input p6 2 /s rdy1 p6 4 /s busy1 pin control bit serial ready output a-d conversion input analog input pin selection bit serial ready input data bus port latch direction register data bus port latch direction register pull-up control pull-up control data bus port latch direction register pull-up control data bus port latch direction register pull-up control data bus port latch direction register (8) port p4 7 int 2 interrupt input data bus
38b5 group user?s manual 1-19 hardware functional description fig. 13 port block diagram (3) (18) ports p8 5 , p8 6 (19) port p8 7 (20) port p9 0 (21) port p9 1 port p9 0 oscillator port xc switch bit (17) port p8 4 (16) port p6 5 sub-clock generating circuit input port xc switch bit p8 7 /pwm output enable bit pwm 0 output rtp output real time port control bit s stb1 output pull-up control (15) port p6 4 data bus s busy1 output int 4 interrupt input, s busy1 input a-d conversion input p6 2 /s rdy1 p6 4 /s busy1 pin control bit p6 5 /s stb1 pin control bit pull-up control port latch direction register analog input pin selection bit data bus port latch direction register a-d conversion input pull-up control port latch direction register data bus local data bus dimmer signal (note) fld/port switch register pull-up control port latch direction register data bus local data bus dimmer signal (note) fld/port switch register pull-up control port latch direction register data bus local data bus dimmer signal (note) fld/port switch register pull-up control port latch direction register data bus port xc switch bit pull-up control port latch direction register data bus * high-breakdown-voltage p-channel transistor note: the dimmer signal sets the toff timing. (14) ports p6 3 , p7 pull-up control data bus port latch direction register a-d conversion input analog input pin selection bit dimmer output control bit (p6 3 ) dimmer signal output (p6 3 )
38b5 group users manual 1-20 hardware functional description interrupts interrupts occur by twenty one sources: five external, fifteen internal, and one software. (1) interrupt control each interrupt except the brk instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the interrupt disable flag is 0. interrupt enable bits can be set or cleared by software. inter- rupt request bits can be cleared by software, but cannot be set by software. the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt and reset. if several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. (2) interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the contents of the program counter and processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. n notes on use when the active edge of an external interrupt (int 0 Cint 4 ) is set or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. therefore, please take following sequence: (1) disable the external interrupt which is selected. (2) change the active edge in interrupt edge selection register (3) clear the set interrupt request bit to 0. (4) enable the external interrupt which is selected.
38b5 group user?s manual 1-21 hardware functional description vector addresses (note 1) interrupt request interrupt source priority remarks high low generating conditions reset (note 2) 1 fffd 16 fffc 16 at reset non-maskable int 0 2 fffb 16 fffa 16 at detection of either rising or falling edge of external interrupt int 0 input (active edge selectable) int 1 3 fff9 16 fff8 16 at detection of either rising or falling edge of external interrupt int 1 input (active edge selectable) int 2 4 fff7 16 fff6 16 at detection of either rising or falling edge of external interrupt int 2 input (active edge selectable) remote control/ at 8-bit counter overflow valid when interrupt interval counter overflow determination is operating serial i/o1 5 fff5 16 fff4 16 at completion of data transfer valid when serial i/o ordinary mode is selected serial i/o auto- at completion of the last data transfer valid when serial i/o automatic matic transfer transfer mode is selected timer x 6 fff3 16 fff2 16 at timer x underflow timer 1 7 fff1 16 fff0 16 at timer 1 underflow timer 2 8 ffef 16 ffee 16 at timer 2 underflow stp release timer underflow timer 3 9 ffed 16 ffec 16 at timer 3 underflow timer 4 10 ffeb 16 ffea 16 at timer 4 underflow (note 3) timer 5 11 ffe9 16 ffe8 16 at timer 5 underflow timer 6 12 ffe7 16 ffe6 16 at timer 6 underflow serial i/o2 receive 13 ffe5 16 ffe4 16 at completion of serial i/o2 data receive int 3 14 ffe3 16 ffe2 16 at detection of either rising or falling edge of external interrupt (note 4) int 3 input (active edge selectable) serial i/o2 transmit at completion of serial i/o2 data transmit int 4 15 ffe1 16 ffe0 16 at detection of either rising or falling edge of external interrupt int 4 input (active edge selectable) valid when int 4 interrupt is selected a-d conversion at completion of a-d conversion valid when a-d conversion is selected fld blanking 16 ffdf 16 ffde 16 at falling edge of the last timing immediately valid when fld blanking before blanking period starts interrupt is selected fld digit at rising edge of digit (each timing) valid when fld digit interrupt is selected brk instruction 17 ffdd 16 ffdc 16 at brk instruction execution non-maskable software interrupt table 8 interrupt vector addresses and priority notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. 3 : in the mask option type p, timer 4 interrupt whose count source is cntr 1 input cannot be used. 4 : in the mask option type p, int 3 interrupt cannot be used.
38b5 group user?s manual 1-22 hardware functional description fig. 15 structure of interrupt related registers interrupt disable flag i interrupt request interrupt request bit interrupt enable bit brk instruction reset fig. 14 interrupt control b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 int 0 interrupt enable bit int 1 interrupt enable bit int 2 interrupt enable bit remote controller/counter overflow interrupt enable bit serial i/o1 interrupt enable bit serial i/o automatic transfer interrupt enable bit timer x interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit int 0 interrupt request bit int 1 interrupt request bit int 2 interrupt request bit remote controller/counter overflow interrupt request bit serial i/o1 interrupt request bit serial i/o automatic transfer interrupt request bit timer x interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit interrupt edge selection register int 0 interrupt edge selection bit int 1 interrupt edge selection bit int 2 interrupt edge selection bit int 3 interrupt edge selection bit (note 1) int 4 interrupt edge selection bit not used (return "0" when read) cntr 0 pin edge switch bit cntr 1 pin edge switch bit (note 1) (intedge : address 003a 16 ) 0 : falling edge active 1 : rising edge active interrupt request register 1 interrupt control register 1 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 (ireq2 : address 003d 16 ) interrupt control register 2 0 : interrupt disabled 1 : interrupt enabled (icon2 : address 003f 16 ) interrupt source switch register int 3 /serial i/o2 transmit interrupt switch bit (note 1) 0 : int 3 interrupt 1 : serial i/o2 transmit interrupt int 4 /ad conversion interrupt switch bit 0 : int 4 interrupt 1 : a-d conversion interrupt not used (return ??when read) (do not write ??to these bits.) (ifr : address 0039 16 ) 0 : rising edge count 1 : falling edge count int 3 /serial i/o2 transmit interrupt enable bit (note 3) int 4 interrupt enable bit ad conversion interrupt enable bit fld blanking interrupt enable bit fld digit interrupt enable bit not used (returns ??when read) (do not write ??to this bit.) int 3 /serial i/o2 transmit interrupt request bit (note 2) int 4 interrupt request bit ad conversion interrupt request bit fld blanking interrupt request bit fld digit interrupt request bit not used (returns ??when read) timer 4 interrupt request bit (note 2) timer 5 interrupt request bit timer 6 interrupt request bit serial i/o2 receive interrupt request bit timer 4 interrupt enable bit (note 3) timer 5 interrupt enable bit timer 6 interrupt enable bit serial i/o2 receive interrupt enable bit notes 1: in the mask option type p, these bits are not available because cntr 1 function and int 3 function cannot be used. 2: in the mask option type p, if timer 4 interrupt whose count source is cntr 1 input and int 3 interrupt are selected, these bits do not become ?? 3: in the mask option type p, timer 4 interrupt whose count source is cntr 1 input and int 3 interrupt are not available.
38b5 group user?s manual 1-23 hardware functional description timer 12 mode register (t12m: address 0028 16 ) timer 1 count stop bit 0 : count operation 1 : count stop timer 2 count stop bit 0 : count operation 1 : count stop timer 1 count source selection bits 00 : f(x in )/8 or f(x cin )/16 01 : f(x cin ) 10 : f(x in )/16 or f(x cin )/32 11 : f(x in )/64 or f(x cin )/128 timer 2 count source selection bits 00 : underflow of timer 1 01 : f(x cin ) 10 : external count input cntr 0 11 : not available timer 1 output selection bit (p4 5 ) 0 : i/o port 1 : timer 1 output not used (returns ??when read) (do not write ??to this bit.) timer 34 mode register (t34m: address 0029 16 ) timer 3 count stop bit 0 : count operation 1 : count stop timer 4 count stop bit 0 : count operation 1 : count stop timer 3 count source selection bits 00 : f(x in )/8 or f(x cin )/16 01 : underflow of timer 2 10 : f(x in )/16 or f(x cin )/32 11 : f(x in )/64 or f(x cin )/128 timer 4 count source selection bits 00 : f(x in )/8 or f(x cin )/16 01 : underflow of timer 3 10 : external count input cntr 1 (note) 11 : not available timer 3 output selection bit (p4 6 ) 0 : i/o port 1 : timer 3 output not used (returns ??when read) (do not write ??to this bit.) timer 56 mode register (t56m: address 002a 16 ) timer 5 count stop bit 0 : count operation 1 : count stop timer 6 count stop bit 0 : count operation 1 : count stop timer 5 count source selection bit 0 : f(x in )/8 or f(x cin )/16 1 : underflow of timer 4 timer 6 operation mode selection bit 0 : timer mode 1 : pwm mode timer 6 count source selection bits 00 : f(x in )/8 or f(x cin )/16 01 : underflow of timer 5 10 : underflow of timer 4 11 : not available timer 6 (pwm) output selection bit (p4 4 ) 0 : i/o port 1 : timer 6 output not used (returns ??when read) (do not write ??to this bit.) b7 b0 b7 b0 b7 b0 note: in the mask option type p, cntr 1 function cannot be used. timers 8-bit timer the 38b5 group has six built-in timers : timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. each timer has the 8-bit timer latch. all timers are down-counters. when the timer reaches ?0 16 ,?an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. when a timer underflows, the interrupt request bit corresponding to that timer is set to ?. the count can be stopped by setting the stop bit of each timer to ?. the internal system clock can be set to either the high-speed mode or low-speed mode with the cpu mode register. at the same time, timer internal count source is switched to either f(x in ) or f(x cin ). l timer 1, timer 2 the count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. a rectangular waveform of timer 1 under- flow signal divided by 2 can be output from the p4 5 /t 1out pin. the active edge of the external clock cntr 0 can be switched with the bit 6 of the interrupt edge selection register. at reset or when executing the stp instruction, all bits of the timer 12 mode register are cleared to ?,?timer 1 is set to ?f 16 ,?and timer 2 is set to ?1 16 . l timer 3, timer 4 the count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. a rectangular waveform of timer 3 under- flow signal divided by 2 can be output from the p4 6 /t 3out pin. the active edge of the external clock cntr 1 (note) can be switched with the bit 7 of the interrupt edge selection register. note: in the mask option type p, cntr 1 function cannot be used. l timer 5, timer 6 the count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. a rectangular waveform of timer 6 under- flow signal divided by 2 can be output from the p4 4 /pwm 1 pin. l timer 6 pwm 1 mode timer 6 can output a pwm rectangular waveform with ??duty cycle n/(n+m) from the p4 4 /pwm 1 pin by setting the timer 56 mode regis- ter (refer to figure 18). the n is the value set in timer 6 latch (address 0025 16 ) and m is the value in the timer 6 pwm register (address 0027 16 ). if n is ?,?the pwm output is ?,?if m is ?,?the pwm output is ??(n = 0 is prior than m = 0). in the pwm mode, interrupts occur at the rising edge of the pwm output. fig. 16 structure of timer related register
38b5 group user?s manual 1-24 hardware functional description fig. 17 block diagram of timer x in 1/8 p4 6 /t3 out 1/2 x cin ? ? ?1 ?0 ?1 ?0 ?1 ?0 ?0 ? ? ?1 ?0 ?0 ?0 ?1 p4 5 /t 1out 1/2 p6 1 /cntr 0 /cntr 2 ?0 1/2 pwm p4 4 /pwm 1 ? ? p6 0 /cntr 1 1/64 1/2 ?1 ?1 1/16 ?0 ?0 internal system clock selection bit timer 1 count source selection bits timer 1 interrupt request data bus timer 1 latch (8) timer 1 (8) ff 16 timer 1 count stop bit reset stp instruction p4 5 latch timer 1 output selection bit p4 5 direction register timer 2 count source selection bits timer 2 latch (8) timer 2 (8) timer 2 count stop bit 01 16 timer 3 count source selection bits timer 3 latch (8) timer 3 (8) timer 3 count stop bit timer 2 interrupt request timer 3 interrupt request p4 6 latch rising/falling active edge switch timer 3 output selection bit p4 6 direction register timer 4 count source selection bits timer 4 latch (8) timer 4 (8) timer 4 count stop bit rising/falling active edge switch timer 4 interrupt request timer 5 count source selection bit timer 5 latch (8) timer 5 (8) timer 5 count stop bit timer 5 interrupt request p4 4 latch timer 6 output selection bit p4 4 direction register timer 6 count source selection bits timer 6 latch (8) timer 6 (8) timer 6 count stop bit timer 6 pwm register (8) timer 6 operation mode selection bit timer 6 interrupt request (note) note: in the mask option type p, cntr 1 function cannot be used.
38b5 group users manual 1-25 hardware functional description fig. 18 timing chart of timer 6 pwm 1 mode ts timer 6 count source timer 6 pwm mode n 5 ts (n+m) 5 ts timer 6 interrupt request note: pwm waveform (duty : n/(n + m) and period: (n + m) 5 ts) is output. n : setting value of timer 6 m: setting value of timer 6 pwm register ts: period of timer 6 count source m 5 ts timer 6 interrupt request
38b5 group users manual 1-26 hardware functional description 16-bit timer timer x is a 16-bit timer that can be selected in one of four modes by the timer x mode registers 1, 2 and can be controlled the timer x write and the real time port by setting the timer x mode registers. read and write operation on 16-bit timer must be performed for both high- and low-order bytes. when reading a 16-bit timer, read from the high-order byte first. when writing to 16-bit timer, write to the low- order byte first. the 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. l timer x timer x is a down-counter. when the timer reaches 0000 16 , an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down- counting. when a timer underflows, the interrupt request bit corre- sponding to that timer is set to 1. (1) timer mode a count source can be selected by setting the timer x count source selection bits (bits 1 and 2) of the timer x mode register 1. (2) pulse output mode each time the timer underflows, a signal output from the cntr 2 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 2 pin to output. (3) event counter mode the timer counts signals input through the cntr 2 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 2 pin to input. (4) pulse width measurement mode a count source can be selected by setting the timer x count source selection bits (bits 1 and 2) of the timer x mode register 1. when cntr 2 active edge switch bit is 0, the timer counts while the input signal of the cntr 2 pin is at h. when it is 1, the timer counts while the input signal of the cntr 2 pin is at l. when using a timer in this mode, set the port shared with the cntr 2 pin to input. n note ?timer x write control if the timer x write control bit is 0, when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1, when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. when the value is written in latch only, unexpected value may be set in the high-order counter if the writing in high-order latch and the underflow of timer x are performed at the same timing. ?real time port control while the real time port function is valid, data for the real time port are output from ports p8 5 and p8 6 each time the timer x underflows. (however, if the real time port control bit is changed from 0 to 1, data are output without the timer x.) when the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer x. before using this function, set the corresponding port direction regis- ters to output mode.
38b5 group users manual 1-27 hardware functional description fig. 20 structure of timer x related registers b7 b0 timer x mode register 1 (txm1 : address 002e 16 ) timer x write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch only timer x count source selection bits b2 b1 0 0 : f(x in )/2 or f(x cin )/4 0 1 : f(x in )/8 or f(x cin )/16 1 0 : f(x in )/64 or f(x cin )/128 1 1 : not available not used (returns "0" when read) timer x operating mode bits b5 b4 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 2 active edge switch bit 0 : ?event counter mode ; counts rising edges ?pulse output mode ; output starts with ??level ?pulse width measurement mode ; measures ??periods 1 : ?event counter mode ; counts falling edges ?pulse output mode ; output starts with ??level ?pulse width measurement mode ; measures ??periods timer x stop control bit 0 : count operating 1 : count stop real time port control bit (p8 5 ) 0 : real time port function is invalid 1 : real time port function is valid real time port control bit (p8 6 ) 0 : real time port function is invalid 1 : real time port function is valid p8 5 data for real time port p8 6 data for real time port not used (returns "0" when read) timer x mode register 2 (txm2 : address 002f 16 ) b7 b0 fig. 19 block diagram of timer x cntr 2 active edge switch bit cntr 2 active edge switch bit real time port control bit real time port control bit s ? ? ? ? ?0 ?0??1??1 q q t p6 1 /cntr 0 /cntr 2 cntr 0 ? ? ? ? ? ? q d q d p8 5 p8 6 ? ? x in x cin @ ? ? 1/2 1/2 1/8 1/64 p6 1 latch timer x (low-order) (8) timer x (high-order) (8) timer x latch (high-order) (8) timer x latch (low-order) (8) data bus pulse output mode p6 1 direction register pulse width measurement mode timer x operating mode bits timer x stop control bit pulse output mode count source selection bit internal system clock selection bit divider timer x write control bit timer x interrupt request timer x mode register write signal p8 6 latch p8 6 direction register p8 5 latch p8 5 direction register latch latch p8 5 data for real time port real time port control bit (p8 5 ) p8 6 data for real time port real time port control bit (p8 6 ) timer x mode register write signal
38b5 group user? manual 1-28 hardware functional description serial i/o l serial i/o1 serial i/o1 is used as the clock synchronous serial i/o and has an ordinary mode and an automatic transfer mode. in the automatic transfer mode, serial transfer is performed through the serial i/o automatic transfer ram which has up to 256 bytes (addresses 0f00 16 to 0fff 16 : addresses 0f60 16 to 0fff 16 are also used as fig. 21 block diagram of serial i/o1 fld automatic display ram). the p6 2 /s rdy1 /an 8 , p6 4 /int 4 /s busy1 /an 10 , and p6 5 /s stb1 /an 11 pins each have a handshake i/o signal function and can select either ??active or ??active for active logic. main data bus serial i/o1 automatic transfer controller local data bus serial i/o automatic transfer ram (0f00 16 ?fff 16 ) serial i/o1 control register 3 x cin x in internal system clock selection bit serial i/o1 automatic transfer data pointer address decoder main address bus local address bus ? ? 1/8 1/16 1/32 1/64 1/128 serial i/o1 interrupt request p6 4 latch serial i/o1 counter synchronous circuit serial i/o1 synchronous clock selection bit ? p6 2 latch p5 2 /s clk11 ? ? s clk1 ? internal synchronous clock selection bits 1/256 p6 5 latch p6 4 /s busy1 p6 5 /s stb1 (p6 5 /s stb1 pin control bit) serial transfer status flag ? ? ? ? p6 2 /s rdy1 ? ? p5 2 latch p5 1 /s out1 p5 0 /s in1 p5 1 latch serial i/o1 register (8) ? ? serial transfer selection bits 1/2 divider 1/4 serial i/o1 clock pin selection bit p5 3 /s clk12 ? ? p5 3 latch ? ? ? ? serial i/o1 clock pin selection bits p6 2 /s rdy1 ?6 4 /s busy1 pin control bit p6 2 /s rdy1 ?6 4 /s busy1 pin control bit
38b5 group users manual 1-29 hardware functional description fig. 22 structure of serial i/o1 control registers 1, 2 b7 b0 p6 2 /s rdy1 ? p6 4 /s busy1 pin control bits 0000: pins p6 2 and p6 4 are i/o ports 0001: not used 0010: p6 2 pin is an s rdy1 output, p6 4 pin is an i/o port. 0011: p6 2 pin is an s rdy1 output, p6 4 pin is an i/o port. 0100: p6 2 pin is an i/o port, p6 4 pin is an s busy1 input. 0101: p6 2 pin is an i/o port, p6 4 pin is an s busy1 input. 0110: p6 2 pin is an i/o port, p6 4 pin is an s busy1 output. 0111: p6 2 pin is an i/o port, p6 4 pin is an s busy1 output. 1000: p6 2 pin is an s rdy1 input, p6 4 pin is an s busy1 output. 1001: p6 2 pin is an s rdy1 input, p6 4 pin is an s busy1 output. 1010: p6 2 pin is an s rdy1 input, p6 4 pin is an s busy1 output. 1011: p6 2 pin is an s rdy1 input, p6 4 pin is an s busy1 output. 1100: p6 2 pin is an s rdy1 output, p6 4 pin is an s busy1 input. 1101: p6 2 pin is an s rdy1 output, p6 4 pin is an s busy1 input. 1110: p6 2 pin is an s rdy1 output, p6 4 pin is an s busy1 input. 1111: p6 2 pin is an s rdy1 output, p6 4 pin is an s busy1 input. serial i/o1 control register 2 (sio1con2 (sc12): address 001a 16 ) p5 1/ s out1 p-channel output disable bit 0: cmos 3-state (p-channel output is valid.) 1: n-channel open-drain (p-channel output is invalid.) s out1 pin control bit (at no-transfer serial data) 0: output active 1: output high-impedance s busy1 output ?s stb1 output function selection bit (valid in automatic transfer mode) 0: functions as each 1-byte signal 1: functions as signal for all transfer data serial transfer status flag 0: serial transfer completion 1: serial transferring b7 b0 serial i/o1 control register 1 (sio1con1 (sc11) : address 0019 16 ) serial i/o1 synchronous clock selection bits (p6 5 /s stb1 pin control bit) 00: internal synchronous clock (p6 5 pin is an i/o port.) 01: external synchronous clock (p6 5 pin is an i/o port.) 10: internal synchronous clock (p6 5 pin is an s stb1 output.) 11: internal synchronous clock (p6 5 pin is an s stb1 output.) transfer mode selection bit 0: full duplex (transmit and receive) mode (p5 0 pin is an s in1 input.) 1: transmit-only mode (p5 0 pin is an i/o port.) serial i/o initialization bit 0: serial i/o initialization 1: serial i/o enabled serial i/o1 clock pin selection bit 0:s clk11 (p5 3/ s clk12 pin is an i/o port.) 1:s clk12 (p5 2/ s clk11 pin is an i/o port.) transfer direction selection bit 0: lsb first 1: msb first serial transfer selection bits 00: serial i/o disabled (pins p6 2 ,p6 4 ,p6 5 ,and p5 0 p5 3 are i/o ports) 01: 8-bit serial i/o 10: not available 11: automatic transfer serial i/o (8-bits)
38b5 group users manual 1-30 hardware functional description (1) serial i/o1 operation either the internal synchronous clock or external synchronous clock can be selected by the serial i/o1 synchronous clock selection bits (b2 and b3 of address 0019 16 ) of serial i/o1 control register 1 as synchronous clock for serial transfer. the internal synchronous clock has a built-in dedicated divider where 7 different clocks are selected by the internal synchronous clock selection bits (b5, b6 and b7 of address 001c 16 ) of serial i/o1 control register 3. the p6 2 /s rdy1 /an 8 , p6 4 /int 4 /s busy1 /an 10, and p6 5 /s stb1 /an 11 pins each select either i/o port or handshake i/o signal by the serial i/o1 synchronous clock selection bits (b2 and b3 of address 0019 16 ) of serial i/o1 control register 1 as well as the p6 2 /s rdy1 ? p6 4 /s busy1 pin control bits (b0 to b3 of address 001a 16 ) of serial i/o1 control register 2. for the s out1 being used as an output pin, either cmos output or n-channel open-drain output is selected by the p5 1 /s out1 p-chan- nel output disable bit (b7 of address 001a 16 ) of serial i/o1 control register 2. either output active or high-impedance can be selected as a s out1 pin state at serial non-transfer by the s out1 pin control bit (b6 of address 001a 16 ) of serial i/o1 control register 2. however, when the external synchronous clock is selected, perform the following setup to put the s out1 pin into a high-impedance state. when the s clk1 input is h after completion of transfer, set the s out1 pin control bit to 1. when the s clk1 input goes to l after the start of the next serial transfer, the s out1 pin control bit is automatically reset to 0 and put into an output active state. regardless of whether the internal synchronous clock or external synchronous clock is selected, the full duplex mode and the trans- mit-only mode are available for serial transfer, one of which is se- lected by the transfer mode selection bit (b5 of address 0019 16 ) of serial i/o1 control register 1. either lsb first or msb first is selected for the i/o sequence of the serial transfer bit strings by the transfer direction selection bit (b6 of address 0019 16 ) of serial i/o1 control register 1. when using serial i/o1, first select either 8-bit serial i/o or auto- matic transfer serial i/o by the serial transfer selection bits (b0 and b1 of address 0019 16 ) of serial i/o1 control register 1, after comple- tion of the above bit setup. next, set the serial i/o initialization bit (b4 of address 0019 16 ) of serial i/o1 control register 1 to 1 (serial i/o enable) . when stopping serial transfer while data is being transferred, re- gardless of whether the internal or external synchronous clock is selected, reset the serial i/o initialization bit (b4) to 0. serial i/o1 control register 3 (sio1con3 (sc13): address 001c 16 ) internal synchronous clock selection bits 000: f(x in )/4 or f(x cin )/8 001: f(x in )/8 or f(x cin )/16 010: f(x in )/16 or f(x cin )/32 011: f(x in )/32 or f(x cin )/64 100: f(x in )/64 or f(x cin )/128 101: f(x in )/128 or f(x cin )/256 110: f(x in )/256 or f(x cin )/512 automatic transfer interval set bits 00000: 2 cycles of transfer clocks 00001: 3 cycles of transfer clocks : 11110: 32 cycles of transfer clocks 11111: 33 cycles of transfer clocks data is written to a latch and read from a decrement counter. b7 b0 fig. 23 structure of serial i/o1 control register 3
38b5 group user? manual 1-31 hardware functional description (2) 8-bit serial i/o mode address 001b 16 is assigned to the serial i/o1 register. when the internal synchronous clock is selected, a serial transfer of the 8-bit serial i/o is started by a write signal to the serial i/o1 register (address 001b 16 ). the serial transfer status flag (b5 of address 001a 16 ) of serial i/o1 control register 2 indicates the shift register status of serial i/o1, and is set to ??by writing into the serial i/o1 register, which be- comes a transfer start trigger and reset to ??after completion of 8- bit transfer. at the same time, a serial i/o1 interrupt request occurs. when the external synchronous clock is selected, the contents of the serial i/o1 register are continuously shifted while transfer clocks are input to s clk1 . therefore, the clock needs to be controlled ex- ternally. (3) automatic transfer serial i/o mode the serial i/o1 automatic transfer controller controls the write and read operations of the serial i/o1 register, so the function of ad- dress 001b 16 is used as a transfer counter (1-byte units). when performing serial transfer through the serial i/o automatic transfer ram (addresses 0f00 16 to 0fff 16 ), it is necessary to set the serial i/o1 automatic transfer data pointer (address 0018 16 ) beforehand. input the low-order 8 bits of the first data store address to be seri- ally transferred to the automatic transfer data pointer set bits. when the internal synchronous clock is selected, the transfer inter- val for each 1-byte data can be set by the automatic transfer inter- val set bits (b0 to b4 of address 001c 16 ) of serial i/o1 control regis- ter 3 in the following cases: 1. when using no handshake signal 2. when using the s rdy1 output, s busy1 output, and s stb1 output of the handshake signal independently 3. when using a combination of s rdy1 output and s stb1 output or a combination of s busy1 output and s stb1 output of the handshake signal it is possible to select one of 32 different values, namely 2 to 33 cycles of the transfer clock, as a setting value. when using the s busy1 output and selecting the s busy1 output s stb1 output function selection bit (b4 of address 001a 16 ) of serial i/o1 control register 2 as the signal for all transfer data, provided that the automatic transfer interval setting is valid, a transfer inter- val is placed before the start of transmission/reception of the first data and after the end of transmission/reception of the last data. for s stb1 output, regardless of the contents of the s busy1 output s stb1 output function selection bit (b4), the transfer interval for each 1-byte data is longer than the set value by 2 cycles. furthermore, when using a combination of s busy1 output and s stb1 output as a signal for all transfer data, the transfer interval after the end of transmission/reception of the last data is longer than the set value by 2 cycles. when the external synchronous clock is selected, automatic trans- fer interval setting is disabled. after completion of the above bit setup, if the internal synchronous clock is selected, automatic serial transfer is started by writing the value of ?umber of transfer bytes - 1?into the transfer counter (address 001b 16 ). when the external synchronous clock is selected, write the value of ?umber of transfer bytes - 1?into the transfer counter and input an internal system clock interval of 5 cycles or more. after that, input transfer clock to s clk1 . as a transfer interval for each 1-byte data transfer, input an internal system clock interval of 5 cycles or more from the clock rise time of the last bit. regardless of whether the internal or external synchronous clock is selected, the automatic transfer data pointer and the transfer counter are decremented after each 1-byte data is received and then written into the automatic transfer ram. the serial transfer status flag (b5 of address 001a 16 ) is set to ??by writing data into the transfer counter. writing data becomes a transfer start trigger, and the serial transfer status flag is reset to ??after the last data is written into the automatic transfer ram. at the same time, a serial i/o1 interrupt request occurs. the values written in the automatic transfer data pointer set bits (b0 to b7 of address 0018 16 ) and the automatic transfer interval set bits (b0 to b4 of address 001c 16 ) are held in the latch. when data is written into the transfer counter, the values latched in the automatic transfer data pointer set bits (b0 to b7) and the auto- matic transfer interval set bits (b0 to b4) are transferred to the decrement counter. fig. 24 structure of serial i/o1 automatic transfer data pointer b7 b0 serial i/o1 automatic transfer data pointer (sio1dp: address 0018 16 ) automatic transfer data pointer set bits specify the low-order 8 bits of the first data store address on the serial i/o automatic transfer ram. data is written into the latch and read from the decrement counter.
38b5 group users manual 1-32 hardware functional description fff 16 automatic transfer ram transfer counter automatic transfer data pointer serial i/o1 register f52 16 f51 16 f50 16 f4f 16 f4e 16 f00 16 04 16 52 16 s in1 s out1 fig. 25 automatic transfer serial i/o operation
38b5 group users manual 1-33 hardware functional description when the external synchronous clock is selected, input an h level signal into the s busy1 input and an l level signal into the s busy1 input in the initial status in which transfer is stopped. at this time, the transfer clocks to be input in s clk1 become invalid. during serial transfer, the transfer clocks to be input in s clk1 be- come valid, enabling a transmit/receive operation, while an l level signal is input into the s busy1 input and an h level signal is input into the s busy1 input. when changing the input values in the s busy1 input and the s busy1 input at these operations, change them when the s clk1 input is in a high state. when the high impedance of the s out1 output is selected by the s out1 pin control bit (b6), the s out1 output becomes active, en- abling serial transfer by inputting a transfer clock to s clk1 , while an l level signal is input into the s busy1 input and an h level signal is input into the s busy1 input. 3. s busy1 output signal the s busy1 output is a signal which requests a stop of transmis- sion/reception to the serial transfer destination. in the automatic transfer serial i/o mode, regardless of the internal or external syn- chronous clock, whether the s busy1 output is to be active at trans- fer of each 1-byte data or during transfer of all data can be selected by the s busy1 output ? s stb1 output function selection bit (b4). in the initial status, the status in which the serial i/o initialization bit (b4) is reset to 0, the s busy1 output goes to h and the s busy1 output goes to l. fig. 27 s busy1 input operation (internal synchronous clock) fig. 28 s busy1 input operation (external synchronous clock) (4) handshake signal 1. s stb1 output signal the s stb1 output is a signal to inform an end of transmission/re- ception to the serial transfer destination . the s stb1 output signal can be used only when the internal synchronous clock is selected. in the initial status, namely, in the status in which the serial i/o initialization bit (b4) is reset to 0, the s stb1 output goes to l, or the s stb1 output goes to h. at the end of transmit/receive operation, when the data of the serial i/o1 register is all output from s out1 , pulses are output in the pe- riod of 1 cycle of the transfer clock so as to cause the s stb1 output to go h or the s stb1 output to go l. after that, each pulse is returned to the initial status in which s stb1 output goes to l or the s stb1 output goes to h. furthermore, after 1 cycle, the serial transfer status flag (b5) is re- set to 0. in the automatic transfer serial i/o mode, whether the s stb1 output is to be active at an end of each 1-byte data or after completion of transfer of all data can be selected by the s busy1 output ? s stb1 output function selection bit (b4 of address 001a 16 ) of serial i/o1 control register 2. 2. s busy1 input signal the s busy1 input is a signal which receives a request for a stop of transmission/reception from the serial transfer destination. when the internal synchronous clock is selected, input an h level signal into the s busy1 input and an l level signal into the s busy1 input in the initial status in which transfer is stopped. when starting a transmit/receive operation, input an l level signal into the s busy1 input and an h level signal into the s busy1 input in the period of 1.5 cycles or more of the transfer clock. then, transfer clocks are output from the s clk1 output. when an h level signal is input into the s busy1 input and an l level signal into the s busy1 input after a transmit/receive operation is started, this transmit/receive operation are not stopped immedi- ately and the transfer clocks from the s clk1 output is not stopped until the specified number of bits are transmitted and received. the handshake unit of the 8-bit serial i/o is 8 bits and that of the automatic transfer serial i/o is 8 bits. fig. 26 s stb1 output operation s stb1 s clk1 s out1 serial transfer status flag s busy1 s clk1 s out1 s busy1 s clk1 s out1 invalid (output high-impedance)
38b5 group users manual 1-34 hardware functional description when the internal synchronous clock is selected, in the 8-bit serial i/o mode and the automatic transfer serial i/o mode (s busy1 out- put function outputs in 1-byte units), the s busy1 output goes to l and the s busy1 output goes to h before 0.5 cycle (transfer clock) of the timing at which the transfer clock from the s clk1 output goes to l at a start of transmit/receive operation. in the automatic transfer serial i/o mode (the s busy1 output func- tion outputs all transfer data), the s busy1 output goes to l and the s busy1 output goes to h when the first transmit data is written into the serial i/o1 register (address 001b 16 ). when the external synchronous clock is selected, the s busy1 out- put goes to l and the s busy1 output goes to h when transmit data is written into the serial i/o1 register to start a transmit opera- tion, regardless of the serial i/o transfer mode. at termination of transmit/receive operation, the s busy1 output re- turns to h and the s busy1 output returns to l, the initial status, when the serial transfer status flag is set to "0", regardless of whether the internal or external synchronous clock is selected. furthermore, in the automatic transfer serial i/o mode (s busy1 out- put function outputs in 1-byte units), the s busy1 output goes to h and the s busy1 output goes to l each time 1-byte of receive data is written into the automatic transfer ram. fig. 29 s busy1 output operation (internal synchronous clock, 8-bits serial i/o) fig. 30 s busy1 output operation (external synchronous clock, 8-bits serial i/o) fig. 31 s busy1 output operation in automatic transfer serial i/o mode (internal synchronous clock, s busy1 output function outputs each 1-byte) s busy1 s clk1 s out1 serial transfer status flag serial transfer status flag s busy1 s clk1 write to serial i/o1 register s clk1 s busy1 s out1 automatic transfer interval serial transfer status flag automatic transfer ram serial i/o1 register serial i/o1 register automatic transfer ram
38b5 group users manual 1-35 hardware functional description 4. s rdy1 output signal the s rdy1 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. in the initial status, when the serial i/o initialization bit (b4) is reset to 0, the s rdy1 output goes to l and the s rdy1 output goes to h. after transmitted data is stored in the serial i/o1 register (address 001b 16 ) and a transmit/receive operation becomes ready, the s rdy1 output goes to h and the s rdy1 output goes to l. when a transmit/ receive operation is started and the transfer clock goes to l, the s rdy1 output goes to l and the s rdy1 output goes to h. 5. s rdy1 input signal the s rdy1 input signal becomes valid only when the s rdy1 input and the s busy1 output are used. the s rdy1 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. when the internal synchronous clock is selected, input a low level signal into the s rdy1 input and a high level signal into the s rdy1 input in the initial status in which the transfer is stopped. when an h level signal is input into the s rdy1 input and an l level signal is input into the s rdy1 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the s clk1 output and a transmit/receive operation is started. after the transmit/receive operation is started and an l level sig- nal is input into the s rdy1 input and an h level signal into the s rdy1 input, this operation cannot be immediately stopped. after the specified number of bits are transmitted and received, the transfer clocks from the s clk1 output is stopped. the handshake unit of the 8-bit serial i/o and that of the automatic transfer serial i/o are of 8 bits. when the external synchronous clock is selected, the s rdy1 input becomes one of the triggers to output the s busy1 signal. to start a transmit/receive operation (s busy1 output: l, s busy1 output: h), input an h level signal into the s rdy1 input and an l level signal into the s rdy1 input, and also write transmit data into the serial i/o1 register. fig. 32 s rdy1 output operation fig. 33 s rdy1 input operation (internal synchronous clock) s rdy1 s clk1 write to serial i/o1 register s rdy1 s clk1 s out1
38b5 group users manual 1-36 hardware functional description a: b: s clk1 s rdy1 s busy1 s busy1 s rdy1 s clk1 a: b: write to serial i/o1 register s clk1 s rdy1 s busy1 internal synchronous clock selection external synchronous clock selection write to serial i/o1 register a: b: s clk1 s rdy1 s busy1 s busy1 s rdy1 s clk1 a: b: write to serial i/o1 register s clk1 s rdy1 s busy1 internal synchronous clock selection external synchronous clock selection write to serial i/o1 register fig. 34 handshake operation at serial i/o1 mutual connecting (1) fig. 35 handshake operation at serial i/o1 mutual connecting (2)
38b5 group users manual 1-37 hardware functional description d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transmit/receive shift clock (1/2 1/2048 of internal clock or external clock) serial i/o2 output txd serial i/o2 input rxd write-in signal to serial i/o2 transmit/receive buffer register (address 001f 16 ) overrun error (oe) detection notes 1 : the transmit interrupt (ti) can be selected to occur either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting transmit interrupt source selection bit (tic) of the serial i/o2 control register. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ?. receive enable signal s rdy2 l serial i/o2 serial i/o2 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation during serial i/o2 operation. (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode can be selected by setting the serial i/o2 mode selection bit (b6) of the serial i/o2 control reg- fig. 37 operation of clock synchronous serial i/o2 function fig. 36 block diagram of clock synchronous serial i/o2 ister (address 001d 16 ) to 1. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock for serial i/o2 operation. if an internal clock is used, transmit/receive is started by a write signal to the serial i/o2 transmit/receive buffer register (tb/ rb) (address 001f 16 ). when p5 7 (s clk22 ) is selected as a clock i/o pin, s rdy2 output function is invalid, and p5 6 (s clk21 ) is used as an i/o port. 1/4 1/4 f/f p5 6 /s clk21 p5 4 /r x d p5 5 /t x d p5 7 /s rdy2 / s clk22 ? ? ? ? x in 1/2 x cin ? ? p5 7 /s rdy2 / s clk22 serial i/o2 status register serial i/o2 control register receive buffer register address 001f 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o2 synchronous clock selection bit baud rate generator division ratio 1/(n+1) address 0016 16 brg count source selection bit clock control circuit falling edge detector transmit buffer register data bus address 001f 16 shift clock transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 001e 16 data bus address 001d 16 transmit shift register serial i/o2 clock i/o pin selection bit internal system clock selection bit brg clock switch bit serial i/o2 clock i/o pin selection bit
38b5 group users manual 1-38 hardware functional description oe pe fe 1/16 1/16 transmit buffer register clock control circuit p5 6 /s clk21 p5 4 /r x d p5 5 /t x d p5 7 /s rdy2 /s clk22 ? ? 1/4 ? ? x in 1/2 x cin ? data bus receive buffer register address 001f 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator division ratio 1/(n+1) address 0016 16 st/sp/pa generator data bus transmit shift register address 001f 16 transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 001e 16 st detector uart control register address 0017 16 character length selection bit address 001d 16 brg count source selection bit transmit interrupt source selection bit serial i/o2 synchronous clock selection bit character length selection bit 7 bit 8 bit serial i/o2 control register serial i/o2 status register sp detector serial i/o2 clock i/o pin selection bit internal system clock selection bit brg clock switch bit (2) asynchronous serial i/o (uart) mode the asynchronous serial i/o (uart) mode can be selected by clear- ing the serial i/o2 mode selection bit (b6) of the serial i/o2 control register (address 001d 16 ) to 0. eight serial data transfer formats can be selected and the transfer formats used by the transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer can receive 2-byte data continuously. fig. 39 operation of uart serial i/o2 function fig. 38 block diagram of uart serial i/o2 tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1* st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock * generated at 2nd bit in 2-stop bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit serial i/o2 input r x d write-in signal to transmit buffer register serial i/o2 output t x d read-out signal from receive buffer register
38b5 group users manual 1-39 hardware functional description [serial i/o2 control register] sio2con (001d 16 ) the serial i/o2 control register contains eight control bits for serial i/o2 functions. [uart control register] uartcon (0017 16 ) this is a 7 bit register containing four control bits, which are valid when uart is selected, two control bits, which are valid when using serial i/o2, and one control bit, which is always valid. data format of serial data receive/transfer and the output structure of the p5 5 /txd pin, etc. are set by this register. [serial i/o2 status register] sio2sts (001e 16 ) the read-only serial i/o2 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial i/o2 function and various errors. three of the flags (b4 to b6) are only valid in the uart mode. the receive buffer full flag (b1) is cleared to 0 when the receive buffer is read. the error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a writing to the serial i/o2 status regis- ter clears error flags oe, pe, fe, and se (b3 to b6, respectively). writing 0 to the serial i/o2 enable bit (sioe : b7 of the serial i/o2 control register) also clears all the status flags, including the error flags. all bits of the serial i/o2 status register are initialized to 0 at reset, but if the transmit enable bit (b4) of the serial i/o2 control register has been set to 1, the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become 1. [serial i/o2 transmit buffer register/receive buffer register] tb/rb (001f 16 ) the transmit buffer and the receive buffer are located in the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is "0". [baud rate generator] brg (0016 16 ) the baud rate generator determines the baud rate for serial transfer. with the 8-bit counter having a reload register, the baud rate genera- tor divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. fig. 40 structure of serial i/o2 related register b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift register shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns "1" when read) serial i/o2 status register (sio2sts : address 001e 16 ) serial i/o2 control register (sio2con : address 001d 16 ) b0 b0 b7 uart control register (uartcon : address 0017 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p5 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) brg clock switch bit 0: x in or x cin (depends on internal system clock) 1: x cin serial i/o2 clock i/o pin selection bit 0: s clk21 (p5 7 /s clk22 pin is used as i/o port or s rdy2 output pin.) 1: s clk22 (p5 6 /s clk21 pin is used as i/o port.) not used (return "1" when read) b0 brg count source selection bit (css) 0: f(x in ) or f(x cin )/2 or f(x cin ) 1: f(x in )/4 or f(x cin )/8 or f(x cin )/4 serial i/o2 synchronous clock selection bit (scs) 0: brg/ 4 (when clock synchronous serial i/o is selected) brg/16 (uart is selected) 1: external clock input (when clock synchronous serial i/o is selected) external clock input/16 (uart is selected) s rdy2 output enable bit (srdy) 0: p5 7 pin operates as ordinary i/o pin 1: p5 7 pin operates as s rdy2 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o2 mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o2 enable bit (sioe) 0: serial i/o2 disabled (pins p5 4 to p5 7 operate as ordinary i/o pins) 1: serial i/o2 enabled (pins p5 4 to p5 7 operate as serial i/o pins)
38b5 group users manual 1-40 hardware functional description fld controller the 38b5 group has fluorescent display (fld) drive and control cir- cuits. the fld controller consists of the following components: ?40 pins for fld control pins ?fldc mode register ?fld data pointer ?fld data pointer reload register ?tdisp time set register ?toff1 time set register ?toff2 time set register ?port p0fld/port switch register ?port p2fld/port switch register ?port p8fld/port switch register ?port p8 fld output control register ?fld automatic display ram (max. 160 bytes) a gradation display mode can be used for bright/dark display as a display function. fig. 41 block diagram for fld control circuit p2 0 /fld 0 p2 1 /fld 1 p2 2 /fld 2 p2 3 /fld 3 p2 4 /fld 4 p2 5 /fld 5 p2 6 /fld 6 p2 7 /fld 7 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 0004 16 0efa 16 8 0000 16 0ef9 16 8 p0 0 /fld 8 p0 1 /fld 9 p0 2 /fld 10 p0 3 /fld 11 p0 4 /fld 12 p0 5 /fld 13 p0 6 /fld 14 p0 7 /fld 15 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 0002 16 8 p1 0 /fld 16 p1 1 /fld 17 p1 2 /fld 18 p1 3 /fld 19 p1 4 /fld 20 p1 5 /fld 21 p1 6 /fld 22 p1 7 /fld 23 0006 16 8 p3 0 /fld 24 p3 1 /fld 25 p3 2 /fld 26 p3 3 /fld 27 p3 4 /fld 28 p3 5 /fld 29 p3 6 /fld 30 p3 7 /fld 31 0010 16 0efb 16 8 p8 0 /fld 32 p8 1 /fld 33 p8 2 /fld 34 p8 3 /fld 35 p8 4 /fld 36 p8 5 /fld 37 p8 6 /fld 38 p8 7 /fld 39 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 0f60 16 0fff 16 main address bus local address bus fld automatic display ram main data bus local data bus fld blanking interrupt fld digit interrupt fldc mode register (0ef4 16 ) fld data pointer reload register (0ef8 16 ) fld data pointer (0ef8 16 ) timing generator address decoder
38b5 group users manual 1-41 hardware functional description [fldc mode register] fldm the fldc mode register is a 8-bit register respectively which is used to control the fld automatic display and to set the blanking time tscan for key-scan. fig. 42 structure of fldc mode register fldc mode register (fldm: address 0ef4 16 ) automatic display control bit (p0, p1, p2, p3, p8) 0 : general-purpose mode 1 : automatic display mode display start bit 0 : stop display 1 : display (start to display by switching ??to ?? tscan control bits 00 : fld digit interrupt (at rising edge of each digit) 01 : 1 5 tdisp 10 : 2 5 tdisp 11 : 3 5 tdisp timing number control bit 0 : 16 timing mode 1 : 32 timing mode gradation display mode selection control bit 0 : not selecting 1 : selecting ( note ) tdisp counter count source selection bit 0 : f(x in )/16 or f(x cin )/32 1 : f(x in )/64 or f(x cin )/128 high-breakdown voltage port drivability selection bit 0 : drivability strong 1 : drivability weak b7 b0 fld blanking interrupt (at falling edge of the last digit) notes 1: when a gradation display mode is selected, a number of timing is max. 16 timing. (set the timing number control bit to ?.? 2: when changing bit 4 (timing number control bit) or bit 5 (gradation display mode selection control bit), set ??to bit 1 (display start bit) to perform at display stop state.
38b5 group users manual 1-42 hardware functional description fig. 43 segment/digit setting example fld automatic display pins when the automatic display control bits of the fldc mode register (address 0ef4 16 ) are set to 1, the ports of p0, p1, p2, p3 and p8 are used as fld automatic display pins. when using the fld automatic display mode, set each port to the fld pin or the general-purpose port using the respective switch reg- ister in accordance with the number of segments and the number of digits. this setting is performed by writing a value into the fld/port switch register (addresses 0ef9 16 to 0efb 16 ) of each port. this setting can be performed in units of bit. when 0 is set, the port is set to the general-purpose port. when 1 is set, the port is set to the fld pin. there is no restriction on whether the fld pin is to be used as a segment pin or a digit pin. table 9 pins in fld automatic display mode port name automatic display pins setting method p0, p2, fld 0 Cfld 15 the individual bits of the fld/port switch register (addresses 0ef9 16 C0efb 16 ) can be set each pin p8 0 Cp8 3 fld 32 Cfld 35 either fld port (1) or general-purpose port (0). p1, p3 fld 16 Cfld 31 none (fld only) p8 4 Cp8 7 fld 36 Cfld 39 the individual bits of the fld/port switch register (address 0efb 16 ) can be set each pin to either fld port (1) or general-purpose port (0). the output can be reversed by the port p8 fld output control register (address 0efc 16 ). the port output format is the cmos output format. when using the port as a display pin, a driver must be installed externally. 15 8 p2 4 p2 5 p2 6 p2 7 p2 0 p2 1 p2 2 p2 3 0 0 0 0 0 0 0 0 fld 16 (dig 1 ) fld 17 (dig 2 ) fld 18 (dig 3 ) fld 19 (dig 4 ) fld 20 (seg 4 ) fld 21 (seg 5 ) fld 22 (seg 6 ) fld 23 (seg 7 ) p0 4 p0 5 fld 14 (seg 2 ) fld 15 (seg 3 ) fld 8 (seg 1 ) p0 1 p0 2 p0 3 1 0 0 0 0 0 1 1 fld 32 (seg 12 ) fld 33 (seg 13 ) fld 34 (seg 14 ) fld 35 (seg 15 ) p8 4 p8 5 p8 6 p8 7 fld 24 (seg 8 ) fld 25 (seg 9 ) fld 26 (seg 10 ) fld 27 (seg 11 ) fld 28 (dig 5 ) fld 29 (dig 6 ) fld 30 (dig 7 ) fld 31 (dig 8 ) 1 1 1 1 0 0 0 0 25 15 fld 8 (seg 9 ) fld 9 (seg 10 ) fld 10 (seg 11 ) fld 11 (seg 12 ) fld 12 (seg 13 ) fld 13 (seg 14 ) fld 14 (seg 15 ) fld 15 (seg 16 ) 1 1 1 1 1 1 1 1 fld 0 (seg 1 ) fld 1 (seg 2 ) fld 2 (seg 3 ) fld 3 (seg 4 ) fld 4 (seg 5 ) fld 5 (seg 6 ) fld 6 (seg 7 ) fld 7 (seg 8 ) fld 16 (dig 1 ) fld 17 (dig 2 ) fld 18 (dig 3 ) fld 19 (dig 4 ) fld 20 (dig 5 ) fld 21 (dig 6 ) fld 22 (dig 7 ) fld 23 (dig 8 ) 1 1 1 1 1 1 1 1 fld 24 (dig 9 ) fld 25 (dig 10 ) fld 26 (dig 11 ) fld 27 (dig 12 ) fld 28 (dig 13 ) fld 29 (dig 14 ) fld 30 (dig 15 ) fld 31 (seg 17 ) fld 32 (seg 18 ) fld 33 (seg 19 ) fld 34 (seg 20 ) fld 35 (seg 21 ) 1 1 1 1 1 1 1 1 fld 36 (seg 22 ) fld 37 (seg 23 ) fld 38 (seg 24 ) fld 39 (seg 25 ) 18 20 fld 8 (dig 1 ) fld 9 (dig 2 ) fld 10 (dig 3 ) fld 11 (dig 4 ) fld 12 (dig 5 ) fld 13 (dig 6 ) fld 14 (dig 7 ) fld 15 (dig 8 ) 1 1 1 1 1 1 fld 2 (seg 1 ) fld 3 (seg 2 ) fld 4 (seg 3 ) fld 5 (seg 4 ) fld 6 (seg 5 ) fld 7 (seg 6 ) fld 16 (dig 9 ) fld 17 (dig 10 ) fld 18 (dig 11 ) fld 19 (dig 12 ) fld 20 (dig 13 ) fld 21 (dig 14 ) fld 22 (dig 15 ) fld 23 (dig 16 ) 1 1 1 1 1 1 1 1 fld 24 (dig 17 ) fld 25 (dig 18 ) fld 26 (dig 19 ) fld 27 (dig 20 ) fld 28 (seg 7 ) fld 29 (seg 8 ) fld 32 (seg 11 ) fld 33 (seg 12 ) fld 34 (seg 13 ) fld 35 (seg 14 ) 1 1 1 1 1 1 1 1 fld 36 (seg 15 ) fld 37 (seg 16 ) fld 38 (seg 17 ) fld 39 (seg 18 ) 16 10 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p2 0 p2 1 p2 2 p2 3 fld 4 (seg 1 ) fld 5 (seg 2 ) fld 6 (seg 3 ) fld 7 (seg 4 ) fld 8 (seg 5 ) fld 9 (seg 6 ) fld 10 (seg 7 ) fld 11 (seg 8 ) fld 12 (seg 9 ) fld 13 (seg 10 ) fld 14 (seg 11 ) fld 15 (seg 12 ) fld 16 (dig 1 ) fld 17 (dig 2 ) fld 18 (dig 3 ) fld 19 (dig 4 ) fld 20 (dig 5 ) fld 21 (dig 6 ) fld 22 (dig 7 ) fld 23 (dig 8 ) fld 24 (dig 9 ) fld 25 (dig 10 ) fld 26 (seg 13 ) fld 27 (seg 14 ) fld 28 (seg 15 ) fld 29 (seg 16 ) p8 1 p8 0 p8 2 p8 3 p8 4 p8 5 p8 6 p8 7 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 p2 0 p2 1 fld 30 (seg 9 ) fld 31 (seg 10 ) 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 p2 4 p2 5 number of segments number of digits port p2 setting example 1 setting example 2 setting example 3 setting example 4 port p0 port p1 port p3 port p8 value of fldram write disable register if data is set to ?? data is protected. this setting does not decide the fld port function (seg/dig). value of fld/port switch register
38b5 group users manual 1-43 hardware functional description fld automatic display ram the fld automatic display ram uses the 160 bytes of addresses 0f60 16 to 0fff 16 . for fld, the 3 modes of 16-timing ordinary mode, 16-timing?gradation display mode and 32-timing mode are available depending on the number of timings and the presence/absence of gradation display. the automatic display ram in each mode is as follows: (1) 16-timing?ordinary mode the 80 bytes of addresses 0fb0 16 to 0fff 16 are used as a fld display data store area. because addresses 0f60 16 to 0faf 16 are not used as the automatic display ram, they can be the ordi- nary ram or serial i/o automatic transfer ram. (2) 16-timing?gradation display mode the 160 bytes of addresses 0f60 16 to 0fff 16 are used. the 80 bytes of addresses 0fb0 16 to 0fff 16 are used as an fld dis- play data store area, while the 80 bytes of addresses 0f60 16 to 0faf 16 are used as a gradation display control data store area. (3) 32-timing mode the 160 bytes of addresses 0f60 16 to 0fff 16 are used as an fld display data store area. [fld data pointer and fld data pointer reload register] flddp (0ef8 16 ) both the fld data pointer and fld data pointer reload register are 8-bit registers assigned at address 0ef8 16 . when writing data to this address, the data is written to the fld data pointer reload register; when reading data from this address, the value in the fld data pointer is read. fig. 44 fld automatic display ram assignment 16-timing?rdinary mode 0fff 16 0fb0 16 0f60 16 0fff 16 0f60 16 0fff 16 0fb0 16 0f60 16 16-timing?radation display mode 32-timing mode 1 to 32 timing display data stored area gradation display control data stored area 1 to 16 timing display data stored area 1 to 16 timing display data stored area not used
38b5 group users manual 1-44 hardware functional description data setup (1) 16-timing?ordinary mode the area of addresses 0fb0 16 to 0fff 16 are used as a fld automatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p2 is stored at address 0fb0 16 , the last data of fld port p0 is stored at address 0fc0 16 , the last data of fld port p1 is stored at address 0fd0 16 , the last data of fld port p3 is stored at address 0fe0 16 , and the last data of fld port p8 is stored at address 0ff0 16 , to assign in sequence from the last data respectively. the first data of the fld port p2, p0, p1, p3, and p8 is stored at an address which adds the value of (the timing number C 1) to the corresponding address 0fb0 16 , 0fc0 16 , 0fd0 16 , 0fe0 16 , and 0ff0 16 . set the fld data pointer reload register to the value given by the timing number C 1. 1 is always written to bits 7, 6, and 5. note that 0 is always read from bits 7, 6, and 5 when reading. 1 is always set to bit 4, but this bit become written value when read- ing. (2) 16-timing?gradation display mode display data setting is performed in the same way as that of the 16-timing?ordinary mode. gradation display control data is ar- ranged at an address resulting from subtracting 0050 16 from the display data store address of each timing and pin. bright dis- play is performed by setting 0, and dark display is performed by setting 1. set the fld data pointer reload register to the value given by the timing number C 1. 1 is always written to bits 7, 6, and 5. note that 0 is always read from bits 7, 6, and 5 when reading. 1 is always set to bit 4, but this bit become written value when read- ing. (3) 32-timing mode the area of addresses 0f60 16 to 0fff 16 are used as a fld au- tomatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p2 is stored at address 0f60 16 , the last data of fld port p0 is stored at address 0f80 16 , the last data of fld port p1 is stored at address 0fa0 16 , the last data of fld port p3 is stored at address 0fc0 16 , and the last data of fld port p8 is stored at address 0fe0 16 , to assign in sequence from the last data respectively. the first data of the fld port p2, p0, p1, p3, and p8 is stored at an address which adds the value of (the timing number C 1) to the corresponding address 0f60 16 , 0f80 16 , 0fa0 16 , 0fc0 16 , and 0fe0 16 . set the fld data pointer reload register to the value given by the timing number C1. 1 is always written to bits 7, 6, and 5. note that 0 is always read from bits 7, 6, and 5 when reading. fig. 45 example of using fld automatic display ram in 16-timing?ordinary mode number of fld segments: 15 number of timing: 8 (fld data pointer reload register = 7) address 0fcf 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 0fca 16 0fcb 16 0fcc 16 0fcd 16 0fce 16 0fd0 16 0fd1 16 0fd2 16 0fd3 16 0fd4 16 0fd5 16 0fd6 16 0fd7 16 0fd8 16 0fd9 16 0fda 16 0fdb 16 0fdc 16 0fdd 16 0fde 16 0fdf 16 0fe1 16 0fe2 16 0fe3 16 0fe4 16 0fe5 16 0fe6 16 0fe7 16 0fe8 16 0fe9 16 0fea 16 0feb 16 0fec 16 0fed 16 0fee 16 0fef 16 0fe0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 0ff7 16 0ff8 16 0ff9 16 0ffa 16 0ffb 16 0ffc 16 0ffd 16 0ffe 16 0fff 16 0ff0 16 0fb0 16 the last timing (the last data of fldp2) 76543210 bit the last timing (the last data of fldp0) the last timing (the last data of fldp1) the last timing (the last data of fldp3) the last timing (the last data of fldp8) timing for start (the first data of fldp2) fldp2 data area timing for start (the first data of fldp0) fldp0 data area timing for start (the first data of fldp1) fldp1 data area timing for start (the first data of fldp3) fldp3 data area timing for start (the first data of fldp8) fldp8 data area note: shaded area is used for segment. shaded area is used for digit.
38b5 group users manual 1-45 hardware functional description fig. 46 example of using fld automatic display ram in 16-timing?gradation display mode 0fcf 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 0fca 16 0fcb 16 0fcc 16 0fcd 16 0fce 16 0fd0 16 0fd1 16 0fd2 16 0fd3 16 0fd4 16 0fd5 16 0fd6 16 0fd7 16 0fd8 16 0fd9 16 0fda 16 0fdb 16 0fdc 16 0fdd 16 0fde 16 0fdf 16 0fe1 16 0fe2 16 0fe3 16 0fe4 16 0fe5 16 0fe6 16 0fe7 16 0fe8 16 0fe9 16 0fea 16 0feb 16 0fec 16 0fed 16 0fee 16 0fef 16 0fe0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 0ff7 16 0ff8 16 0ff9 16 0ffa 16 0ffb 16 0ffc 16 0ffd 16 0ffe 16 0fff 16 0ff0 16 0fb0 16 0f7f 16 0f60 16 0f61 16 0f62 16 0f63 16 0f64 16 0f65 16 0f66 16 0f67 16 0f68 16 0f69 16 0f6a 16 0f6b 16 0f6c 16 0f6d 16 0f6e 16 0f6f 16 0f70 16 0f71 16 0f72 16 0f73 16 0f74 16 0f75 16 0f76 16 0f77 16 0f78 16 0f79 16 0f7a 16 0f7b 16 0f7c 16 0f7d 16 0f7e 16 7654 210 0f80 16 0f81 16 0f82 16 0f83 16 0f84 16 0f85 16 0f86 16 0f87 16 0f88 16 0f89 16 0f8a 16 0f8b 16 0f8c 16 0f8d 16 0f8e 16 0f8f 16 0f91 16 0f92 16 0f93 16 0f94 16 0f95 16 0f96 16 0f97 16 0f98 16 0f99 16 0f9a 16 0f9b 16 0f9c 16 0f9d 16 0f9e 16 0f9f 16 0f90 16 0fa1 16 0fa2 16 0fa3 16 0fa4 16 0fa5 16 0fa6 16 0fa7 16 0fa8 16 0fa9 16 0faa 16 0fab 16 0fac 16 0fad 16 0fae 16 0faf 16 0fa0 16 3 76543210 bit address number of fld segments: 25 number of timing: 15 (fld data pointer reload register = 14) the last timing (the last data of fldp2) note: shaded area is used for segment. shaded area is used for digit. fldp2 data area timing for start (the first data of fldp2) the last timing (the last data of fldp0) fldp0 data area timing for start (the first data of fldp0) the last timing (the last data of fldp1) fldp1 data area timing for start (the first data of fldp1) the last timing (the last data of fldp3) fldp3 data area timing for start (the first data of fldp3) the last timing (the last data of fldp8) fldp8 data area timing for start (the first data of fldp8) bit address the last timing (the last data of fldp2) fldp2 gradation display data area timing for start (the first data of fldp2) the last timing (the last data of fldp0) fldp0 gradation display data area timing for start (the first data of fldp0) the last timing (the last data of fldp1) fldp1 gradation display data area timing for start (the first data of fldp1) the last timing (the last data of fldp3) fldp3 gradation display data area timing for start (the first data of fldp3) the last timing (the last data of fldp8) fldp8 gradation display data area timing for start (the first data of fldp8) note: shaded area is used for gradation display data.
38b5 group users manual 1-46 hardware functional description fig. 47 example of using fld automatic display ram in 32-timing mode 0f7f 16 0f60 16 0f61 16 0f62 16 0f63 16 0f64 16 0f65 16 0f66 16 0f67 16 0f68 16 0f69 16 0f6a 16 0f6b 16 0f6c 16 0f6d 16 0f6e 16 0f6f 16 0f70 16 0f71 16 0f72 16 0f73 16 0f74 16 0f75 16 0f76 16 0f77 16 0f78 16 0f79 16 0f7a 16 0f7b 16 0f7c 16 0f7d 16 0f7e 16 7654 21 0f80 16 0f81 16 0f82 16 0f83 16 0f84 16 0f85 16 0f86 16 0f87 16 0f88 16 0f89 16 0f8a 16 0f8b 16 0f8c 16 0f8d 16 0f8e 16 0f8f 16 bit address 0f91 16 0f92 16 0f93 16 0f94 16 0f95 16 0f96 16 0f97 16 0f98 16 0f99 16 0f9a 16 0f9b 16 0f9c 16 0f9d 16 0f9e 16 0f9f 16 0f90 16 0fa1 16 0fa2 16 0fa3 16 0fa4 16 0fa5 16 0fa6 16 0fa7 16 0fa8 16 0fa9 16 0faa 16 0fab 16 0fac 16 0fad 16 0fae 16 0faf 16 0fa0 16 3 0 76543210 bit address 0fcf 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 0fca 16 0fcb 16 0fcc 16 0fcd 16 0fce 16 0fd0 16 0fd1 16 0fd2 16 0fd3 16 0fd4 16 0fd5 16 0fd6 16 0fd7 16 0fd8 16 0fd9 16 0fda 16 0fdb 16 0fdc 16 0fdd 16 0fde 16 0fdf 16 0fe1 16 0fe2 16 0fe3 16 0fe4 16 0fe5 16 0fe6 16 0fe7 16 0fe8 16 0fe9 16 0fea 16 0feb 16 0fec 16 0fed 16 0fee 16 0fef 16 0fe0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 0ff7 16 0ff8 16 0ff9 16 0ffa 16 0ffb 16 0ffc 16 0ffd 16 0ffe 16 0fff 16 0ff0 16 0fb0 16 number of fld segments: 18 number of timing: 20 (fld data pointer reload register = 19) the last timing (the last data of fldp3) note: shaded area is used for segment. shaded area is used for digit. fldp3 data area timing for start (the first data of fldp1) timing for start (the first data of fldp3) the last timing (the last data of fldp8) fldp8 data area timing for start (the first data of fldp8) the last timing (the last data of fldp2) fldp2 data area timing for start (the first data of fldp2) the last timing (the last data of fldp0) fldp0 data area timing for start (the first data of fldp0) the last timing (the last data of fldp1) fldp1 data area
38b5 group users manual 1-47 hardware functional description digit data protect function the fld automatic display ram is provided with a data protect function that disables the ram area data to be rewritten as digit data. this function can disable data from being written in optional bits in the ram area corresponding to p1 to p3. a programming load can be reduced by protecting an area that requires no change after data such as digit data is written. write digit data beforehand; then set 1 in the corresponding bits. with this, the setting is completed. the data protect area becomes the maximum ram area of p1 and p3. for example, when bit 0 of p1 is protected in the 16- timing?ordinary mode, bits 0 of ram addresses 0fd0 16 to 0fdf 16 can be protected. likewise, in the 16-timing?gradation display mode, bits 0 of addresses 0fd0 16 to 0fdf 16 and 0f80 16 to 0f8f 16 can be protected. in the 32-timing mode, bits 0 of addresses 0fa0 16 to 0fbf 16 can be protected. fig. 48 structure of fldram write disable register b7 b0 p1fldram write disable register (p1fldram : address 0ef2 16 ) fldram corresponding to p1 0 fldram corresponding to p1 1 fldram corresponding to p1 2 fldram corresponding to p1 3 fldram corresponding to p1 4 fldram corresponding to p1 5 fldram corresponding to p1 6 fldram corresponding to p1 7 b7 b0 0: operating normally 1: write disabled p3fldram write disable register (p3fldram : address 0ef3 16 ) fldram corresponding to p3 0 fldram corresponding to p3 1 fldram corresponding to p3 2 fldram corresponding to p3 3 fldram corresponding to p3 4 fldram corresponding to p3 5 fldram corresponding to p3 6 fldram corresponding to p3 7 0: operating normally 1: write disabled
38b5 group users manual 1-48 hardware functional description fig. 50 example of using fld automatic display ram using grid scan type setting method when using the grid scan type fld when using the grid scan type fld, set 1 in the ram area corre- sponding to the digit ports that output 1 at each timing. set 0 in the ram area corresponding to the other digit ports. fig. 49 example of digit timing using grid scan type dig10 (p3 1 ) dig9 (p3 0 ) dig8 (p1 7 ) dig2 (p1 1 ) dig1 (p1 0 ) number of timing: 10 the first second third.......................9th 10th segment output 0fcf 16 0fb0 16 0fb1 16 0fb2 16 0fb3 16 0fb4 16 0fb5 16 0fb6 16 0fb7 16 0fb8 16 0fb9 16 0fba 16 0fbb 16 0fbc 16 0fbd 16 0fbe 16 0fbf 16 0fc0 16 0fc1 16 0fc2 16 0fc3 16 0fc4 16 0fc5 16 0fc6 16 0fc7 16 0fc8 16 0fc9 16 0fca 16 0fcb 16 0fcc 16 0fcd 16 0fce 16 7654 210 0fd0 16 0fd1 16 0fd2 16 0fd3 16 0fd4 16 0fd5 16 0fd6 16 0fd7 16 0fd8 16 0fd9 16 0fda 16 0fdb 16 0fdc 16 0fdd 16 0fde 16 0fdf 16 bit address 0fe1 16 0fe2 16 0fe3 16 0fe4 16 0fe5 16 0fe6 16 0fe7 16 0fe8 16 0fe9 16 0fea 16 0feb 16 0fec 16 0fed 16 0fee 16 0fef 16 0fe0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 0ff7 16 0ff8 16 0ff9 16 0ffa 16 0ffb 16 0ffc 16 0ffd 16 0ffe 16 0fff 16 0ff0 16 3 1 1 1 1 1 1 1 1 1 1 0000000 0000000 0000000 0000000 000000 000000 00000 00000 0000 0000 000 000 00 00 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 number of fld segments: 16 number of timing: 10 (fld data pointer reload register = 9) the last timing (the last data of fldp2) note: shaded area is used for segment. shaded area is used for digit. fldp2 data area timing for start (the first data of fldp2) the last timing (the last data of fldp0) fldp0 data area timing for start (the first data of fldp0) the last timing (the last data of fldp1) fldp1 data area timing for start (the first data of fldp1) the last timing (the last data of fldp3) fldp3 data area timing for start (the first data of fldp3) the last timing (the last data of fldp8) fldp8 data area timing for start (the first data of fldp8)
38b5 group users manual 1-49 hardware functional description timing setting each timing is set by the fldc mode register, tdisp time set regis- ter, toff1 time set register, and toff2 time set register. ?tdisp time setting set the tdisp time by the tdisp counter count source selection bit of the fldc mode register and the tdisp time set register. supposing that the value of the tdisp time set register is n, the tdisp time is represented as tdisp = (n+1) 5 t (t: count source synchronization). when the tdisp counter count source selection bit of the fldc mode register is 0 and the value of the tdisp time set register is 200 (c8 16 ), the tdisp time is: tdisp = (200+1) 5 4 (at x in = 4 mhz) = 804 s. when reading the tdisp time set register, the value in the counter is read out. ?toff1 time setting set the toff1 time by the toff1 time set register. supposing that the value of the toff1 time set register is n1, the toff1 time is represented as toff1 = n1 5 t. when the tdisp counter count source selection bit of the fldc mode register is 0 and the value of the toff1 time set register is 30 (1e 16 ), toff1 = 30 5 4 (at x in = 4 mhz) = 120 s. set a value of 03 16 or more to the toff1 time set register (address 0ef6 16 ). ?toff2 time setting set the toff2 time by the toff2 time set register. supposing that the value of the toff2 time set register is n2, the toff2 time is represented as toff2 = n2 5 t. when the tdisp counter count source selection bit of the fldc mode register is 0 and the value of the toff2 time set register is 180 (b4 16 ), toff2 = 180 5 4 (at x in = 4 mhz) = 720 s. this toff2 time setting is valid only for fld ports which are in the gradation display mode and whose gradation display control ram value is 1. when setting 1 to bit 7 of the p8fld output control register (ad- dress 0efc 16 ), set a value of 03 16 or more to the toff2 time set register (address 0ef7 16 ). fld automatic display start to perform fld automatic display, set the following registers. ?port p0fld/port switch register ?port p2fld/port switch register ?port p8fld/port switch register ?fldc mode register ?tdisp time set register ?toff1 time set register ?toff2 time set register ?fld data pointer fld automatic display mode is selected by writing 1 to the bit 0 of the fldc mode register (address 0ef4 16 ), and the automatic dis- play is started by writing 1 to bit 1. during fld automatic display, bit 1 of the fldc mode register (address 0ef4 16 ) always keeps 1, and fld automatic display can be interrupted by writing 0 to bit 1. key-scan when a key-scan is performed with the segment during key-scan blanking period tscan, take the following sequence: 1. write 0 to bit 0 of the fldc mode register (address 0ef4 16 ). 2. set the port corresponding to the segment for key-scan to the output port. 3. perform the key-scan. 4. after the key-scan is performed, write 1 to bit 0 of fldc mode register (address 0ef4 16 ). n note when performing a key-scan according to the above step 1 to 4, take the following points into consideration. 1. do not set 0 in bit 1 of the fldc mode register (address 0ef4 16 ). 2. do not set 1 in the ports corresponding to digits.
38b5 group users manual 1-50 hardware functional description fig. 51 fldc timing toff1 tdisp segment digit segment digit output segment setting by software fld blanking interrupt request occurs at the falling edge of the last timing. fld digit interrupt request occurs at the rising edge of digit (each timing). tdisp tscan repeat synchronous tn tn-1 tn-2 t4 t3 t2 t1 toff1 toff2 segment digit when a gradation display mode is selected pin under the condition that bit 5 of the fldc mode register is ?,?and the corresponding gradation display control data value is ?. tdisp n: number of timing
38b5 group users manual 1-51 hardware functional description p8 4 to p8 7 fld output reverse function p8 4 to p8 7 are provided with a function to reverse the polarity of the fld output. this function is useful in adjusting the polarity when using an externally installed driver. the output polarity can be reversed by setting 1 to bit 0 of the port p8 fld output control register. p8 4 to p8 7 fldram write disable function this function can disable writing data in the ram area correspond- ing to p8 4 to p8 7 . this function can be set by setting 1 to bit 1 of the port p8fld output control register (address 0efc 16 ). p8 4 to p8 7 toff invalid function p8 4 to p8 7 can output waveform in which toff is invalid, when p8 4 to p8 7 is selected fld ports (see figure 52). the function is useful when using a 4 bits ? 16 bits decoder. the toff can be invalid by setting 1 to bit 2 of the port p8fld output control register (address 0efc 16 ). p8 4 to p8 7 output delay function p8 4 to p8 7 can output waveform in which is delayed for 16 m s, when selecting fld port and selecting toff invalid function (see figure 52). when using a 4 bits ? 16 bits decoder, the function can be use- ful for prevention of leak radiation caused by phase discrepancy be- tween segment output waveform and digit output waveform. this func- tion can be set by setting 1 to bit 3 of the port p8fld output control register (address 0efc 16 ). dimmer signal output function p6 3 can output the dimmer signal. when using a 4 bits ? 16 bits decoder, the dimmer signal can be used as a control signal for a 4 bits ? 16 bits decoder. when using m35501fp, the dimmer signal can be used as the clk signal. the dimmer signal can be output by setting 1 to bit 4 of the port p8fld output control register (address 0efc 16 ). fig. 52 p8 4 to p8 7 fld output waveform toff2 set/reset change function the value of the toff2 time set register is valid when gradation dis- play mode is selected. the fld ports output (set) the data of display ram at the end of the toff1 time and output 0 (reset) at the end of the toff2 time, when bit 7 of the port p8fld output control register is 0. the fld ports output (set) the data of display ram at the end of the toff2 time and output 0 (reset) at the end of tdisp time, when bit 7 of the port p8fld output control register is 1. fig. 53 structure of port p8 fld output control register port p8fld output control register (p8fldcon: address 0efc 16 ) p8 4 Cp8 7 fld output reverse bit 0: output normally 1: reverse output p8 4 Cp8 7 fldram write disable bit 0: operating normally 1: write disabled p8 4 Cp8 7 toff invalid bit 0: operating normally 1: toff invalid p8 4 Cp8 7 delay control bit (note) 0: no delay 1: delay p6 3 /an 9 dimmer output control bit 0: ordinary port 1: dimmer output not used (??at reading) toff2 control bit 0: gradation display data is reset at toff2 (set at toff1) 1: gradation display data is set at toff2 (reset at tdisp) b7 b0 note: valid only when selecting fld port and p8 4 ?8 7 toff invalid function s e g m e n t d i g i t a t t o f f 2 c o n t r o l b i t = 0 i n g r a d a t i o n d i s p l a y m o d e ( a t g r a d a t i o n d i s p l a y c o n t r o l d a t a = 1 ) t d i s p t o f f 2 t o f f 1 1 6 m s p 8 4 e p 8 7 t o f f i n v a l i d p 8 4 e p 8 7 t o f f i n v a l i d d e l a y d i m m e r s i g n a l a t t o f f 2 c o n t r o l b i t = 1 i n g r a d a t i o n d i s p l a y m o d e ( a t g r a d a t i o n d i s p l a y c o n t r o l d a t a = 1 )
38b5 group users manual 1-52 hardware functional description a-d converter the 38b5 group has a 10-bit a-d converter. the a-d converter per- forms successive approximation conversion. [a-d conversion register] ad one of these registers is a high-order register, and the other is a low- order register. the high-order 8 bits of a conversion result is stored in the a-d conversion register (high-order) (address 0034 16 ), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the a-d conversion register (low-order) (address 0033 16 ). during a-d conversion, do not read these registers. [a-d control register] adcon this register controls a-d converter. bits 3 to 0 are analog input pin selection bits. bit 4 is an ad conversion completion bit and 0 during a-d conversion. this bit is set to 1 upon completion of a-d conver- sion. a-d conversion is started by setting 0 in this bit. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref , and outputs the divided voltages. [channel selector] the channel selector selects one of the input ports p7 7 /an 7 Cp7 0 / an 0 , and p6 5 /s stb1 /an 11 Cp6 2 /s rdy1 /an 8 and inputs it to the com- parator. when port p6 4 is selected as an analog input pin, an external inter- rupt function (int 4 ) is invalid. [comparator and control circuit] the comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad fig. 55 block diagram of a-d converter conversion interrupt request bit to 1. note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 250 khz during a-d conversion. use a cpu system clock dividing the main clock x in as the internal system clock. fig. 54 structure of a-d control register ad conversion result stored bits a-d conversion register (high-order) (adh: address 0034 16 ) b7 b0 analog input pin selection bits 0000: p7 0 /an 0 0001: p7 1 /an 1 0010: p7 2 /an 2 0011: p7 3 /an 3 0100: p7 4 /an 4 0101: p7 5 /an 5 0110: p7 6 /an 6 0111: p7 7 /an 7 1000: p6 2 /s rdy1 /an 8 1001: p6 3 /an 9 1010: p6 4 /int 4 /s busy1 /an 10 1011: p6 5 /s stb1 /an 11 a-d control register (adcon: address 0032 16 ) ad conversion completion bit 0: conversion in progress 1: conversion completed not used (returns ??when read) b7 b0 not used (returns ??when read) ad conversion result stored bits a-d conversion register (low-order) (adl: address 0033 16 ) b7 b0 data bus av ss @ v ref a-d interrupt request b7 b0 4 p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 p6 2 /s rdy1 /an 8 p6 3 /an 9 p6 4 /int 4 /s busy1 /an 10 p6 5 /s stb1 /an 11 a-d control register channel selector comparator a-d control circuit a-d conversion register (h) a-d conversion register (l) (address 0034 16 ) (address 0033 16 ) resistor ladder
38b5 group users manual 1-53 hardware functional description pulse width modulation (pwm) the 38b5 group has a pwm function with a 14-bit resolution. when the oscillation frequency x in is 4 mhz, the minimum resolution bit width is 250 ns and the cycle period is 4096 s. the pwm timing generator supplies a pwm control signal based on a signal that is the frequency of the x in clock. the explanation in the rest assumes x in = 4 mhz. fig. 56 pwm block diagram 14 1/2 x in (4mhz) p8 7 /pwm 0 bit7 bit0 bit5 msb lsb pwm bit7 bit0 data bus x cin ? ? pwm register (high-order) (address 0014 16 ) pwm register (low-order) (address 0015 16 ) it is set to ?? when write. pwm latch (14-bit) 14-bit pwm circuit when an internal system clock selection bit is set to ? timing generating unit for pwm (64 m s cycle) (4096 m s cycle) p8 7 /pwm output selection bit p8 7 direction register p8 7 /pwm output selection bit p8 7 latch
38b5 group users manual 1-54 hardware functional description 1. data setup the pwm output pin also function as port p8 7 . set port p8 7 to be the pwm output pin by setting bit 0 of the pwm control register (address 0026 16 ) to 1. the high-order 8 bits of output data are set in the high-order pwm register pwmh (address 0014 16 ) and the low-order 6 bits are set in the low-order pwm register pwml (address 0015 16 ). 2. pwm operation the timing of the 14-bit pwm function is shown in figure 57. the 14-bit pwm data is divided into the low-order 6 bits and the high-order 8 bits in the pwm latch. the high-order 8 bits of data determine how long an h level signal is output during each sub-period. there are 64 sub-periods in each period, and each sub-period t is 256 5 t (= 64 s) long. the signals h has a length equal to n times t , and its minimum resolution = 250 ns. the last bit of the sub-period becomes the add bit which is specified either h or l, by the contents of pwml. as shown in table 10, the add bit is decided either h or l. that is, only in the sub-period tm shown in table 10 in the pwm cycle period t = 64t, the h duration is lengthened during the mini- mum resolution width t period in comparison with the other period. for example, if the high-order eight bits of the 14-bit data are 03 16 and the low-order six bits are 05 16 , the length of the h level output in sub-periods t 8 , t 24 , t 32 , t 40 and t 56 is 4 t, and its length 3 t in all other sub-periods. time at the h level of each sub-period almost becomes equal be- cause the time becomes length set in the high-order 8 bits or be- comes the value plus t , and this sub-period t (= 64 m s, approximate 15.6 khz) becomes cycle period approximately. 3. transfer from register to latch data written to the pwml register is transferred to the pwm latch once in each pwm period (every 4096 s), and data written to the pwmh register is transferred to the pwm latch once in each sub- period (every 64 s). when the pwml register is read, the contents of the latch are read. however, bit 7 of the pwml register indicates whether the transfer to the pwm latch is completed; the transfer is completed when bit 7 is 0. table 10 relationship between low-order 6-bit data and setting period of add bit 0 0 0 0 0 0 none 0 0 0 0 0 1 m = 32 0 0 0 0 1 0 m = 16, 48 0 0 0 1 0 0 m = 8, 24, 40, 56 0 0 1 0 0 0 m = 4, 12, 20, 28, 36, 44, 52, 60 0 1 0 0 0 0 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 1 0 0 0 0 0 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63 lsb fig. 57 pwm timing 15.75 m s 64 m s 64 m s 64 m s 64 m s 64 m s m = 0 m = 7 m = 8 m = 9 m = 63 16.0 m s 15.75 m s 15.75 m s 15.75 m s 15.75 m s 15.75 m s pulse width modulation register h: 00111111 pulse width modulation register l: 000101 sub-periods where ??pulse width is 16.0 m s: m = 8, 24, 32, 40, 56 sub-periods where ??pulse width is 15.75 m s: m = all other values 4096 m s sub-periods tm lengthened (m = 0 to 63) low-order 6-bit data
38b5 group user? manual 1-55 hardware functional description fig. 59 14-bit pwm timing fig. 58 structure of pwm control register p8 7 /pwm output selection bit 0: i/o port 1: pwm output not used (return ??when read) pwm control register (pwmcon: address 0026 16 ) b7 b0 6a 6a 6a 6a 6a 6b 6a 6a 6a 6a 6a 6a 6a 6a 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6a 6a 6b 6b 6b 6a 6b 6b 6b 6a 6b 6b 6b 6a 6a 6a 6a 6a 6a 6a 6a 6a 6a 6a 6a 6a 6a 4 3 4 4 3 4 4 3 4 6b 6a 69 68 67 02 01 6a 69 68 67 02 01 02 01 00 ff fe fd 97 96 95 02 01 00 fc ff fe fd 97 96 95 fc add add 1653 16 1a93 16 1aa4 16 1aa4 16 1ee4 16 1ef5 16 t = 4096 m s t = 64 m s 13 16 a4 16 24 16 35 16 7b 16 6a 16 59 16 data 35 16 stored at address 0015 16 t = 64 m s t = 0.25 m s ??period length specified by pwmh 1 2 b5 16 2 pwm register (high-order) pwm register (low-order) pwm latch (14-bit) data 6a 16 stored at address 0014 16 data 24 16 stored at address 0015 16 bit 7 cleared after transfer transfer from register to latch data 7b 16 stored at address 0014 16 transfer from register to latch when bit 7 of pwml is ?,?transfer from register to latch is disabled. pwm output (example 1) low-order 6-bits output h = 6a 16 l = 24 16 6b 16 ............36 times (107) 6a 16 ............28 times (106) pwm output (example 2) low-order 6 bits output h = 6a 16 l = 18 16 6b 16 ............24 times 6a 16 ............40 times pwm output 8-bit counter the add portions with additional t are determined either ??or ??by low-order 6-bit data. minimum bit width (64 64 m s) 5 106 5 64 + 24 (256 0.25 m s) 256 (64 m s), fixed t 106 5 64 + 36 5 ......... .......... .......... .......... .......... ............
38b5 group users manual 1-56 hardware functional description interrupt interval determination function the 38b5 group has an interrupt interval determination circuit. this interrupt interval determination circuit has an 8-bit binary up counter. using this counter, it determines a duration of time from the rising edge (falling edge) of an input signal pulse on the p4 7 /int 2 pin to the rising edge (falling edge) of the signal pulse that is input next. how to determine the interrupt interval is described below. 1. enable the int 2 interrupt by setting bit 2 of the interrupt control register 1 (address 003e 16 ). select the rising interval or falling interval by setting bit 2 of the interrupt edge selection register (address 003a 16 ). 2. set bit 0 of the interrupt interval determination control register (address 0031 16 ) to 1 (interrupt interval determination operat- ing). 3. select the sampling clock of 8-bit binary up counter by setting bit 1 of the interrupt interval determination control register. when writing 0, f(x in )/128 is selected (the sampling interval: 32 s at f(x in ) = 4.19 mhz); when 1, f(x in )/256 is selected (the sampling interval: 64 s at f(x in ) = 4.19 mhz). 4. when the signal of polarity which is set on the int 2 pin (rising or falling edge) is input, the 8-bit binary up counter starts count- ing up of the selected counter sampling clock. 5. when the signal of polarity above 4 is input again, the value of the 8-bit binary up counter is transferred to the interrupt interval determination register (address 0030 16 ), and the remote control interrupt request occurs. immediately after that, the 8-bit binary up counter continues to count up again from 00 16 . 6. when count value reaches ff 16 , the 8-bit binary up counter stops counting up. then, simultaneously when the next counter sam- pling clock is input, the counter sets value ff 16 to the interrupt interval determination register to generate the counter overflow interrupt request. fig. 60 interrupt interval determination circuit block diagram noise filter the p4 7 /int 2 pin builds in the noise filter. the noise filter operation is described below. 1. select the sampling clock of the input signal with bits 2 and 3 of the interrupt interval determination control register. when not using the noise filter, set 00. 2. the p4 7 /int 2 input signal is sampled in synchronization with the selected clock. when sampling the same level signal in a series of three sampling, the signal is recognized as the interrupt signal, and the interrupt request occurs. when setting bit 4 of interrupt interval determination control register to 1, the interrupt request can occur at both rising and falling edges. when using the noise filter, set the minimum pulse width of the int 2 input signal to 3 cycles or more of the sample clock. note: in the low-speed mode (cm 7 = 1), the interrupt interval deter- mination function cannot operate. f(x in )/128 f(x in )/256 1/128 1/64 1/32 f(x in ) counter sampling clock selection bit int 2 interrupt input noise filter 8-bit binary up counter interrupt interval determination register address 0030 16 data bus divider one-sided/both-sided detection selection bit noise filter sampling clock selection bit counter overflow interrupt request or remote control interrupt request
38b5 group user? manual 1-57 hardware functional description fig. 63 interrupt interval determination operation example (at both-sided edge active) fig. 62 interrupt interval determination operation example (at rising edge active) fig. 61 structure of interrupt interval determination control register interrupt interval determination control register (iidcon: address 0031 16 ) interrupt interval determination circuit operating selection bit 0 : stopped 1 : operating counter sampling clock selection bit 0 : f(x in )/128 1 : f(x in )/256 noise filter sampling clock selection bits (int 2 ) 00 : filter stop 01 : f(x in )/32 10 : f(x in )/64 11 : f(x in )/128 one-sided/both-sided edge detection selection bit 0 : one-sided edge detection 1 : both-sided edge detection (can be used when using a noise filter) not used (return ??when read) b7 b0 remote control interrupt request 0 1 2 3 4 5 6 1 2 3 0 fe ff n ff 0 ff 6 6 n 1 n (when iidcon 4 = ?? noise filter sampling clock int 2 pin acceptance of interrupt counter sampling clock 8-bit binary up counter value interrupt interval determination register value remote control interrupt request counter overflow interrupt request 0 1 1 0 fe ff 2 ff 2 3 3 ff 2 n n n 3 2 2 2 0 1 2 1 0 1 0 2 remote control interrupt request (when iidcon 4 = ?? noise filter sampling clock int 2 pin acceptance of interrupt counter sampling clock 8-bit binary up counter value interrupt interval determination register value remote control interrupt request counter overflow interrupt request remote control interrupt request remote control interrupt request
38b5 group users manual 1-58 hardware functional description fig. 65 structure of watchdog timer control register 0, the underflow signal of watchdog timer l becomes the count source. the detection time is set then to f(x in ) = 2.1 s at 4 mhz frequency and f(x cin ) = 512 s at 32 khz frequency. when this bit is set to 1, the count source becomes the signal divided by 8 for f(x in ) (or divided by 16 for f(x cin )). the detection time in this case is set to f(x in ) = 8.2 ms at 4 mhz frequency and f(x cin ) = 2 s at 32 khz frequency. this bit is cleared to 0 after resetting. (3) operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 002b 16 ) permits disabling the stp instruction when the watchdog timer is in opera- tion. when this bit is 0, the stp instruction is enabled. when this bit is 1, the stp instruction is disabled. once the stp instruction is executed, an internal resetting occurs. when this bit is set to 1, it cannot be rewritten to 0 by program. this bit is cleared to 0 after resetting. n note when releasing the stop mode, the watchdog timer performs its count operation even in the stop release waiting time. be careful not to cause the watchdog timer h to underflow in the stop release waiting time, for example, by writing data in the watchdog timer control reg- ister (address 002b 16 ) before executing the stp instruction. fig. 64 block diagram of watchdog timer watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). the watchdog timer consists of an 8-bit watch- dog timer l and a 12-bit watchdog timer h. l standard operation of watchdog timer when any data is not written into the watchdog timer control register (address 002b 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 002b 16 ) and an internal reset occurs at an underflow of the watchdog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 002b 16 ) may be started before an underflow. when the watchdog timer control register (address 002b 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watchdog timer h count source selection bit are read. (1) initial value of watchdog timer at reset or writing to the watchdog timer control register (address 002b 16 ), a watchdog timer h is set to fff 16 and a watchdog timer l to ff 16 . (2) watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 002b 16 ) permits selecting a watchdog timer h count source. when this bit is set to x in data bus x cin ? ? internal system clock selection bit (note) ? ? 1/8 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (12) ?ff 16 ?is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: either high-speed, middle-speed or low-speed mode is selected by bit 7 of cpu mode register. stp instruction ?f 16 ?is set when watchdog timer control register is written to. 1/2 b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/8 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 002b 16 ) b7
38b5 group users manual 1-59 hardware functional description buzzer output circuit the 38b5 group has a buzzer output circuit. one of 1 khz, 2 khz and 4 khz (at x in = 4.19 mhz) frequencies can be selected by the buzzer output control register (address 0efd 16 ). either p4 3 /b uz01 or p2 0 / b uz02 /fld 0 can be selected as a buzzer output port by the output port selection bits (b2 and b3 of address 0efd 16 ). the buzzer output is controlled by the buzzer output on/off bit (b4). fig. 66 block diagram of buzzer output circuit fig. 67 structure of buzzer output control register f(x in ) 1/1024 1/2048 1/4096 port latch buzzer output buzzer output on/off bit output port control signal port direction register divider buzzer output control register (buzcon: address 0efd 16 ) output frequency selection bits (x in = 4.19 mhz) 00 : 1 khz (f(x in )/4096) 01 : 2 khz (f(x in )/2048) 10 : 4 khz (f(x in )/1024) 11 : not available output port selection bits 00 : p2 0 and p4 3 function as ordinary ports. 01 : p4 3 /b uz01 functions as a buzzer output. 10 : p2 0 /b uz02 /fld 0 functions as a buzzer output. 11 : not available buzzer output on/off bit 0 : buzzer output off (??output) 1 : buzzer output on not used (return ??when read) b7 b0
38b5 group users manual 1-60 hardware functional description reset circuit ______ to reset the microcomputer, reset pin should be held at an l ______ level for 2 s or more. then the reset pin is returned to an h level (the power source voltage should be between 2.7 v and 5.5 v, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.5 v for v cc of 2.7 v (switching to the high-speed mode, a power source voltage must be between 4.0 v and 5.5 v). fig. 69 reset sequence fig. 68 reset circuit example (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.7 v reset internal reset data f address sync x in : about 4000 cycles x in ? ? ? ? ? fffc fffd ad h , ad l 1: the frequency relation of f(x in ) and f( f ) is f(x in )=4 f( f ). 2: the question marks (?) indicate an undefined state that depends on the previous state. notes ad l ad h
38b5 group users manual 1-61 hardware functional description fig. 70 internal status at reset 00 16 00 16 3f 16 ff 16 ff 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0032 16 5 : not fixed since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. address register contents address register contents 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 ff 16 00 16 00 16 00 16 0000 16 0001 16 0002 16 0004 16 0005 16 0006 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0017 16 0019 16 001a 16 001c 16 001d 16 001e 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0028 16 timer 4 port p0 port p0 direction register port p1 port p2 port p2 direction register port p3 port p4 port p4 direction register port p5 port p5 direction register port p6 port p6 direction register port p7 port p7 direction register port p8 port p8 direction register uart control register serial i/o1 control register 1 serial i/o1 control register 2 serial i/o1 control register 3 serial i/o2 control register serial i/o2 status register timer 1 timer 2 timer 3 timer 5 timer 6 pwm control register timer 12 mode register (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) 00 16 0029 16 timer 34 mode register (33) (35) (36) (37) (38) (39) (40) (41) timer 56 mode register watchdog timer control register timer x (low-order) timer x (high-order) timer x mode register 1 timer x mode register 2 interrupt interval determination control register a-d control register 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 00 16 00 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0ef0 16 0ef1 16 0ef2 16 0ef3 16 0ef4 16 0ef5 16 0ef6 16 0ef7 16 0ef9 16 0efa 16 0efb 16 0efc 16 0efd 16 (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) port p8fld output control register fldc mode register interrupt source switch register interrupt edge selection register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 pull-up control register 1 pull-up control register 2 p1fldram write disable register p3fldram write disable register tdisp time set register toff1 time set register toff2 time set register port p0fld/port switch register port p2fld/port switch register port p8fld/port switch register ff 16 00 16 00 16 00 16 00 16 00 16 00 16 10 16 port p9 port p9 direction register (34) fffc 16 contents (ps) (pc h ) (pc l ) (61) (62) (63) program counter buzzer output control register processor status register fffd 16 contents 1 5 0031 16 00 16 00 16 00 16 00 16 80 16 00 16 00 16 00 16 00 16 80 16 ff 16 01 16 ff 16 010010 0 0 00 16 00 16 00 16 00 16 5 5 5 55 5
38b5 group users manual 1-62 hardware functional description clock generating circuit the 38b5 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer's recommended values. no external resistor is needed between x in and x out since a feedback resistor exists on-chip. however, an external feedback resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. l frequency control (1) middle-speed mode the internal system clock is the frequency of x in divided by 4. after reset, this mode is selected. (2) high-speed mode the internal system clock is the frequency of x in . (3) low-speed mode the internal system clock is the frequency of x cin divided by 2. n note if you switch the mode between middle/high-speed and low-speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(x in ) > 3f(x cin ). (4) low power consumption mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is re- started (by setting the main clock stop bit to 0), set enough time for oscillation to stabilize. by clearing furthermore the x cout drivability selection bit (b3) of cpu mode register to 0, low power consumption operation of less than 200 a (f(x cin ) = 32 khz) can be realized by reducing the drivability between x cin and x cout . at reset or during stp instruction execu- tion this bit is set to 1 and a strong drivability that has an easy oscillation start is set. l oscillation control (1) stop mode if the stp instruction is executed, the internal system clock stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in divided by 8 or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 12 mode register are cleared to 0. set the interrupt enable bits of the timer 1 and timer 2 to disabled (0) before execut- ing the stp instruction. oscillator restarts when an external interrupt is received, but the internal system clock is not supplied to the cpu until timer 1 underflows. this allows time for the clock circuit oscilla- tion to stabilize. (2) wait mode if the wit instruction is executed, the internal system clock stops at an h level. the states of x in and x cin are the same as the state before executing the wit instruction. the internal system clock re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. fig. 71 ceramic resonator circuit fig. 72 external clock input circuit x cin x cout x in x out c in c out c cin c cout rf rd x in x out external oscillation circuit v cc v ss open x cin x cout external oscillation circuit or external pulse open v cc v ss
38b5 group users manual 1-63 hardware functional description fig. 73 clock generating circuit block diagram wit instruction stp instruction timing f (internal clock) s r q stp instruction s r q main clock stop bit ( note 3 ) s r q 1/4 x in x out x cout x cin interrupt request reset interrupt disable flag l 1/2 1/2 port x c switch bit ( note 3 ) ? ? ? timer 1 count source selection bit ( note 2 ) low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode internal system clock selection bit ( notes 1, 3 ) ? ? timer 1 timer 2 timer 2 count source selection bit ( note 2 ) ? main clock division ratio selection bits ( note 3 ) ? ? ? ? notes 1: when low-speed mode is selected, set the port xc switch bit (b4) to ?. 2: refer to the structure of the timer 12 mode register. 3: refer to the structure of the cpu mode register.
38b5 group users manual 1-64 hardware functional description fig. 74 state transitions of system clock cm 4 : port xc switch bit 0: i/o port function 1: x cin -x cout oscillating function cm 5 : main clock (x in - x out ) stop bit 0: oscillating 1: stopped cm 6 : main clock division ratio selection bit 0: f(x in ) (high-speed mode) 1: f(x in )/4 (middle-speed mode) cm 7 : internal system clock selection bit 0: x in ? out selected (middle-/high-speed mode) 1: x cin ? cout selected (low-speed mode) reset cm 4 cm 7 cm 4 cm 5 cm 6 cm 6 cpu mode register (cpum : address 003b 16 ) b7 b4 cm 7 cm 5 cm 6 cm 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cm 4 ? ? cm 4 ? ? ? ? cm 5 ? ? ? ? cm 5 ? ? ? ? ? ? cm 6 cm 6 cm 6 cm 6 cm 7 =0(4 mhz selected) cm 6 =1(middle-speed) cm 5 =0(x in oscillating) cm 4 =0(32 khz stopped) 1: switch the mode by the allows shown between the mode blocks. (do not switch between the mode directly without an allow.) 2: the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: timer operates in the wait mode. 4: when the stop mode is ended, a delay of approximately 1 ms occurs by timer 1 in middle-/high-speed mode. 5: when the stop mode is ended, a delay of approximately 0.25 s occurs by timer 1 in low-speed mode. 6: the example assumes that 4 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal system clock. middle-speed mode ( f =1 mhz) middle-speed mode ( f =1 mhz) cm 7 =0(4 mhz selected) cm 6 =0(high-speed) cm 5 =0(x in oscillating) cm 4 =0(32 khz stopped) high-speed mode ( f =4 mhz) cm 7 =0(4 mhz selected) cm 6 =0(high-speed) cm 5 =0(x in oscillating) cm 4 =1(32 khz oscillating) high-speed mode ( f =4 mhz) cm 7 =1(32 khz selected) cm 6 =0(high-speed) cm 5 =0(x in oscillating) cm 4 =1(32 khz oscillating) low-speed mode ( f =16 khz) cm 7 =1(32 khz selected) cm 6 =0(high-speed) cm 5 =1(x in stopped) cm 4 =1(32 khz oscillating) cm 7 =0(4 mhz selected) cm 6 =1(middle-speed) cm 5 =0(x in oscillating) cm 4 =1(32 khz oscillating) cm 7 =1(32 khz selected) cm 6 =1(middle-speed) cm 5 =0(x in oscillating) cm 4 =1(32 khz oscillating) low-speed mode ( f =16 khz) cm 7 =1(32 khz selected) cm 6 =1(middle-speed) cm 5 =1(x in stopped) cm 4 =1(32 khz oscillating) low-power dissipation mode ( =16 khz) f low-power dissipation mode ( =16 khz) f notes
38b5 group users manual 1-65 hardware notes on programming/notes on use notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. after a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immediately after they have been written. after writing to an interrupt request reg- ister, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations ?to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after executing an adc or sbc instruction, execute at least one instruction before ex- ecuting a sec, clc, or cld instruction. ?in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ?the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. ?the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ?the data transfer instruction (lda, etc.) ?the operation instruction when the index x mode flag (t) is 1 ?the addressing mode which uses the value of a direction register as an index ?the bit-test instruction (bbc or bbs, etc.) to a direction register ?the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direction registers. serial i/o ?using an external clock when using an external clock, input h to the external clock input pin and clear the serial i/o interrupt request bit before executing serial i/o transfer and serial i/o automatic transfer. ?using an internal clock when using an internal clock, set the synchronous clock to the in- ternal clock, then clear the serial i/o interrupt request bit before ex- ecuting a serial i/o transfer and serial i/o automatic transfer. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 250 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the frequency of the internal system clock by the number of cycles needed to ex- ecute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal system clock is the same of the x in frequency in high-speed mode. at stp instruction release at the stp instruction release, all bits of the timer 12 mode register are cleared. the x cout drivability selection bit (the cpu mode register) is set to 1 (high drive) in order to start oscillating. notes on use notes on built-in eprom version the p4 7 pin of the one time prom version or the eprom version functions as the power source input pin of the internal eprom. therefore, this pin is set at low input impedance, thereby being af- fected easily by noise. to prevent a malfunction due to noise, insert a resistor (approx. 5 k w ) in series with the p4 7 pin.
38b5 group users manual 1-66 hardware data required for mask orders/data required for rom writing orders/rom programming method data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical cop- ies) data required for rom writing or- ders the following are necessary when ordering a rom writing: (1) rom writing confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical cop- ies) fig. 75 programming and testing of one time prom version rom programming method the built-in prom of the blank one time prom version and the eprom version can be read or programmed with a general purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. table 11 special programming adapter package name of programming adapter 80p6n-a pca7438f-80a 80d0 pca7438l-80a the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 75 is recommended to verify programming. programming with prom programmer screening (note) (150? for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 ? exceeding 100 hours. note:
38b5 group users manual 1-67 hardware mask option of pull-down resistor (object product: m38b5xmxh-xxxfp) whether built-in pull-down resistors are connected or not to high- breakdown voltage ports p2 0 to p2 7 and p8 0 to p8 3 can be specified in ordering mask rom. the option type can be specified from among 8 types; a to g, p as shown table 12. table 12 mask option type of pull-down resistor a ($41) b ($42) c ($43) d ($44) e ($45) f ($46) g ($47) connective port of pull-down resistor (connected at 1 writing) p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p8 0 p8 1 p8 2 p8 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111 notes 1: the electrical characteristics of high-breakdown voltage ports p2 0 to p2 7 and p8 0 to p8 3 s built-in pull-down resistors are the same as that of high-breakdown voltage ports p0 0 to p0 7 . 2: the absolute maximum ratings of power dissipation may be exceed owing to the number of built-in pull-down resistor. after calculating the power dissipation, specify the option type. 3: one time prom version and eprom version cannot be specified whether built-in pull-down resistors are connected or not likewise option type a. 4: int 3 function and cntr 1 function cannot be used in the option type p. power dissipation calculating method l fixed number depending on microcomputer?s standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 43 v / 900 m a = 48 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v 5 15 ma = 75 mw l fixed number depending on use condition ? apply voltage to v ee pin: vcc C 45 v ? timing number a; digit number b; segment number c ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: d ? all segment number during repeat cycle: c (= a 5 c) ? total number of built-in resistor: for digit; f, for segment; g ? digit pin current value h (ma) ? segment pin current value i (ma) (1) digit pin power dissipation {h 5 b 5 (1Ctoff/tdisp) 5 voltage} / a (2) segment pin power dissipation {i 5 d 5 (1Ctoff/tdisp) 5 voltage} / a (3) pull-down resistor power dissipation (digit) {power dissipation per 1 digit 5 (b 5 f / b) 5 (1Ctoff/tdisp) } / a (4) pull-down resistor power dissipation (segment) { power dissipation per 1 segment 5 (d 5 g / c) 5 (1Ctoff/tdisp) } / a (5) internal circuit power dissipation (cpu, rom, ram etc.) = 75 mw (1) + (2)+ (3) + (4) + (5) = x mw power dissipation calculating example 1 l fixed number depending on microcomputer?s standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 43 v / 900 m a = 48 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v 5 15 ma = 75 mw l fixed number depending on use condition ? apply voltage to v ee pin: vcc C 45 v ? timing number 17; digit number 16; segment number 20 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 31 ? all segment number during repeat cycle: 340 (= 17 5 20) ? total number of built-in resistor: for digit; 16, for segment; 20 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation {18 5 16 5 (1C1/16) 5 2} / 17 = 31.77 mw (2) segment pin power dissipation {3 5 31 5 (1C1/16) 5 2} / 17 = 10.26 mw (3) pull-down resistor power dissipation (digit) (45 C 2) 2 /48 5 (16 5 16/16) 5 (1 C 1/16) / 17 = 33.99 mw (4) pull-down resistor power dissipation (segment) (45 C 2) 2 /48 5 (31 5 20/20) 5 (1 C 1/16) / 17 = 65.86 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 75 mw (1) + (2)+ (3) + (4) + (5) = 217 mw fig. 76 digit timing waveform (1) mask option of pull-down resistor d i g 0 d i g 1 d i g 2 d i g 3 d i g 1 4 d i g 1 5 d i g 1 6 t i m i n g n u m b e r 123 1 61 7 1 5 1 4 t s c a n r e p e a t c y c l e option type restriction p ($50) 1 1 1 1 11 11 (note 4)
38b5 group users manual 1-68 hardware power dissipation calculating example 2 (when 2 or more digit is turned on at same time) l fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 43 v / 900 m a = 48 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v 5 15 ma = 75 mw l fixed number depending on use condition ? apply voltage to v ee pin: vcc C 45 v ? timing number 11; digit number 12; segment number 24 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 114 ? all segment number during repeat cycle: 264 (= 11 5 24) ? total number of built-in resistor: for digit; 10, for segment; 22 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation {18 5 12 5 (1C1/16) 5 2} / 11 = 36.82 mw (2) segment pin power dissipation {3 5 114 5 (1C1/16) 5 2} / 11 = 58.30 mw (3) pull-down resistor power dissipation (digit) (45 C 2) 2 /48 5 (12 5 10/12) 5 (1 C 1/16) / 11 = 32.84 mw (4) pull-down resistor power dissipation (segment) (45 C 2) 2 /48 5 (114 5 22/24) 5 (1 C 1/16) / 11 = 343.08 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 75 mw (1) + (2)+ (3) + (4) + (5) = 547 mw fig. 77 digit timing waveform (2) mask option of pull-down resistor d i g 0 d i g 1 d i g 2 d i g 3 d i g 7 d i g 8 d i g 9 t i m i n g n u m b e r 12 34567 891 01 1 d i g 4 d i g 5 d i g 6 t s c a n r e p e a t c y c l e
1-69 38b5 group users manual hardware functional description supplement interrupt 38b5 group permits interrupts on the basis of 21 sources. it is vector interrupts with a fixed priority system. accordingly, when two or more interrupt requests occur during the same sampling, the table 13 interrupt sources, vector addresses and interrupt priority functional description supplement higher-priority interrupt is accepted first. this priority is determined by hardware, but various priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. for interrupt sources, vector addresses and interrupt priority, refer to table 13. notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. 3 : in the mask option type p, timer 4 interrupt whose count source is cntr 1 input cannot be used. 4 : in the mask option type p, int 3 interrupt cannot be used. interrupt source reset (note 2) int 0 int 1 int 2 remote control/counter overflow serial i/o1 serial i/o1 automatic transfer timer x timer 1 timer 2 timer 3 timer 4 timer 5 timer 6 serial i/o2 receive int 3 serial i/o2 transmit int 4 a-d conversion fld blanking fld digit brk instruction remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when interrupt interval determination is operating valid when serial i/o1 ordinary mode is selected valid when serial i/o1 automatic transfer mode is selected stp release timer underflow (note 3) external interrupt (active edge selectable) (note 4) external interrupt (active edge selectable) valid when int 4 interrupt is selected valid when a-d conversion is selected valid when fld blanking interrupt is selected valid when fld digit interrupt is selected non-maskable software interrupt priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 vector addresses (note 1) high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16
1-70 38b5 group users manual hardware functional description supplement timing after interrupt the interrupt processing routine begins with the machine cycle fol- lowing the completion of the instruction that is currently in execution. figure 78 shows a timing chart after an interrupt occurs, and figure 79 shows the time up to execution of the interrupt processing routine. fig. 78 timing chart after interrupt occurs fig. 79 time up to execution of interrupt processing routine p c h p c l p sa l a h s , s p ss - 2 , s p s s - 1 , s p s p c b l b h a l , a h a d d r e s s b u s d a t a b u s n o t u s e d : c p u o p e r a t i o n c o d e f e t c h c y c l e ( t h i s i s a n i n t e r n a l s i g n a l w h i c h c a n n o t b e o b s e r v e d f r o m t h e e x t e r n a l u n i t . ) : v e c t o r a d d r e s s o f e a c h i n t e r r u p t : j u m p d e s t i n a t i o n a d d r e s s o f e a c h i n t e r r u p t : 0 0 1 6 o r 0 1 1 6 s y n c b l , b h a l , a h s p s w r r d s y n c f 7 t o 2 3 c y c l e s ( 4 m h z , 1 . 7 5 m s t o 5 . 7 5 m s ) i n t e r r u p t r e q u e s t o c c u r s m a i n r o u t i n e i n t e r r u p t p r o c e s s i n g r o u t i n e 2 c y c l e s5 c y c l e s w a i t i n g t i m e f o r p i p e l i n e p o s t - p r o c e s s i n g p u s h o n t o s t a c k v e c t o r f e t c h i n t e r r u p t o p e r a t i o n s t a r t s 0 t o 1 6 c y c l e s
1-71 38b5 group users manual hardware functional description supplement a-d converter a-d conversion is started by setting ad conversion completion bit to 0. during a-d conversion, internal operations are performed as fol- lows. 1. after the start of a-d conversion, a-d conversion register goes to 00 16 . 2. the highest-order bit of a-d conversion register is set to 1, and the comparison voltage vref is input to the comparator. then, v ref is compared with analog input voltage v in . 3. as a result of comparison, when v ref < v in , the highest-order bit of a-d conversion register becomes 1. when v ref > v in , the high- est-order bit becomes 0. by repeating the above operations up to the lowest-order bit of the a-d conversion register, an analog value converts into a digital value. a-d conversion completes at 61 clock cycles (15.25 m s at f(x in ) = 8 mhz) after it is started, and the result of the conversion is stored into the a-d conversion register. concurrently with the completion of a-d conversion, a-d conversion interrupt request occurs, so that the ad conversion interrupt request bit is set to 1. table 14 relative formula for a reference voltage v ref of a-d converter and v ref v ref 1024 ] 1C ] 10: a result of the first comparison to the tenth comparison table 15 change of a-d conversion register during a-d conversion at start of conversion first comparison second comparison third comparison after completion of tenth comparison 0 a result of a-d conversion ] 1 change of a-d conversion register 0 value of comparison voltage (v ref ) v ref 2 v ref 2 v ref 4 v ref 2 v ref 4 v ref 8 when n = 0 v ref = 0 when n = 1 to 1023 v ref = 5 n n: value of a-d converter (decimal numeral) v ref 2 v ref 4 v ref 1024 ? ? ? ? 00 000 000 0 100 000 0000 10 0000000 ] 1 ] 2 00 0 0000 1 ] 1 ] 2 ] 3 ] 4 ] 5 ] 6 ] 7 ] 8 ] 9 ] 10
1-72 38b5 group users manual hardware functional description supplement figures 80 shows the a-d conversion equivalent circuit, and figure 81 shows the a-d conversion timing chart. fig. 80 a-d conversion equivalent circuit fig. 81 a-d conversion timing chart v s s v c c v s s v c c a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 v r e f v s s v r e f v i n a b o u t 2 k w c b 1 b 2b 0 b 3 a n 8 a n 9 a n 1 0 a n 1 1 a - d c o n t r o l r e g i s t e r b u i l t - i n d - a c o n v e r t e r r e f e r e n c e c l o c k a - d c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) a d c o n v e r s i o n i n t e r r u p t r e q u e s t c h o p p e r a m p l i f i e r s a m p l i n g c l o c k a - d c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) w r i t e s i g n a l f o r a - d c o n t r o l r e g i s t e r a d c o n v e r s i o n c o m p l e t i o n b i t s a m p l i n g c l o c k f 6 1 c y c l e s
chapter 2 chapter 2 application 2.1 i/o port 2.2 timer 2.3 serial i/o 2.4 fld controller 2.5 a-d converter 2.6 pwm 2.7 interrupt interval determination function 2.8 watchdog timer 2.9 buzzer output circuit 2.10 reset circuit 2.11 clock generating circuit
2-2 38b5 group users manual application 2.1 i/o port 2.1 i/o port this paragraph describes the setting method of i/o port relevant registers, notes etc. 2.1.1 memory assignment fig. 2.1.1 memory assignment of i/o port relevant registers pull-up control register 1 (pull1) pull-up control register 2 (pull2) port p7 (p7) port p6 direction register (p6d) port p6 (p6) 0ef0 16 0ef1 16 000e 16 000d 16 port p7 direction register (p7d) 000f 16 port p8 (p8) 0010 16 port p8 direction register (p8d) 0011 16 port p9 (p9) port p9 direction register (p9d) 0012 16 000c 16 port p5 direction register (p5d) port p5 (p5) port p4 direction register (p4d) 000b 16 000a 16 0009 16 port p4 (p4) 0008 16 0007 16 port p3 (p3) port p2 direction register (p2d) port p2 (p2) 0006 16 0005 16 0004 16 0003 16 port p1 (p1) port p0 direction register (p0d) port p0 (p0) 0002 16 0001 16 0000 16 address 0013 16
2-3 application 2.1 i/o port 38b5 group users manual 2.1.2 relevant registers fig. 2.1.2 structure of port pi (i = 0, 1, 2, 3, 4, 5, 7, 8) port pi b7 b6 b5 b4 b3 b2 b1 b0 port pi (i = 0, 1, 2, 3, 4, 5, 7, 8) (pi: addresses 00 16 , 02 16 , 04 16 , 06 16 , 08 16 , 0a 16 , 0e 16 , 10 16 ) b 0 0 port pi 0 l in output mode write port latch read port latch l in input mode write port latch read value of pin port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 functions name at reset r w 1 0 2 0 3 0 4 0 5 0 6 0 7 0 port p6 b7 b6 b5 b4 b3 b2 b1 b0 port p6 (p6: address 0c 16 ) b 0 0 port p6 0 l in output mode write port latch read port latch l in input mode write port latch read value of pin port p6 1 port p6 2 port p6 3 port p6 4 port p6 5 functions name at reset r w 1 0 2 0 3 0 4 0 5 0 6 0 7 0 55 55 nothing is arranged for these bits. when these bits are read out, the contents are undefined. fig. 2.1.3 structure of port p6 port p9 b7 b6 b5 b4 b3 b2 b1 b0 port p9 (p9: address 12 16 ) b 0 0 port p9 0 l in output mode write port latch read port latch l in input mode write port latch read value of pin port p9 1 functions name at reset r w 1 0 2 0 0 0 0 0 0 4 5 6 7 3 nothing is arranged for these bits. when these bits are read out, the contents are undefined. 55 55 55 55 55 55 fig. 2.1.4 structure of port p9
2-4 38b5 group user? manual application 2.1 i/o port fig. 2.1.5 structure of port pi (i = 0, 2, 4, 5, 7, 8) direction register port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (i = 0, 2, 4, 5, 7, 8) (pid: addresses 01 16 , 05 16 , 09 16 , 0b 16 , 0f 16 , 11 16 ) 0 : port pi 0 input mode 1 : port pi 0 output mode b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 : port pi 1 input mode 1 : port pi 1 output mode 0 0 : port pi 2 input mode 1 : port pi 2 output mode 0 0 : port pi 3 input mode 1 : port pi 3 output mode 0 0 : port pi 4 input mode 1 : port pi 4 output mode 0 0 : port pi 5 input mode 1 : port pi 5 output mode 0 0 : port pi 6 input mode 1 : port pi 6 output mode 0 0 : port pi 7 input mode 1 : port pi 7 output mode (note) 0 port pi direction register note: bit 7 of the port p4 direction register (address 09 16 ) does not have direction register function because p4 7 is input port. when writing to bit 7 of the port p4 direction register, write ??to the bit. port p6 direction register b7 b6 b5 b4 b3 b2 b1 b0 port p6 direction register (p6d: address 0d 16 ) 0 : port p6 0 input mode 1 : port p6 0 output mode b 0 1 2 3 4 5 name 0 functions at reset r w 0 : port p6 1 input mode 1 : port p6 1 output mode 0 0 : port p6 2 input mode 1 : port p6 2 output mode 0 0 : port p6 3 input mode 1 : port p6 3 output mode 0 0 : port p6 4 input mode 1 : port p6 4 output mode 0 0 : port p6 5 input mode 1 : port p6 5 output mode 0 port p6 direction register 6 0 7 0 55 55 nothing is arranged for these bits. when these bits are read out, the contents are undefined. fig. 2.1.6 structure of port p6 direction register
2-5 application 2.1 i/o port 38b5 group user? manual fig. 2.1.7 structure of port p9 direction register port p9 direction register b7 b6 b5 b4 b3 b2 b1 b0 port p9 direction register (p9d: address 13 16 ) 0 : port p9 0 input mode 1 : port p9 0 output mode b 0 1 2 3 4 5 name 0 functions at reset r w 0 : port p9 1 input mode 1 : port p9 1 output mode 0 0 0 0 0 port p9 direction register 6 0 7 0 55 55 nothing is arranged for these bits. when these bits are read out, the contents are undefined. 0 0 55 55 55 55 fig. 2.1.8 structure of pull-up control register 1 pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 pull-up control register 1 (pull1: address 0ef0 16 ) b 0 1 2 3 4 5 7 name 0 functions at reset r w 0 0 0 0 0 0 ports p5 0 , p5 1 pull- up control ports p5 2 , p5 3 pull- up control ports p5 6 , p5 7 pull- up control port p6 1 pull-up control ports p6 2 , p6 3 pull- up control nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? ports p5 4 , p5 5 pull- up control 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 6 0 ports p6 4 , p6 5 pull- up control 0: no pull-up 1: pull-up note: the pin set to output port is cut off from pull-up control.
2-6 38b5 group users manual application 2.1 i/o port fig. 2.1.9 structure of pull-up control register 2 2.1.3 terminate unused pins table 2.1.1 termination of unused pins pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 pull-up control register 2 (pull2: address 0ef1 16 ) b 0 1 2 3 4 5 7 name 0 functions at reset r w 0 0 0 0 0 0 ports p7 0 , p7 1 pull- up control ports p7 2 , p7 3 pull- up control ports p7 6 , p7 7 pull- up control ports p8 4 , p8 5 pull- up control ports p8 6 , p8 7 pull- up control nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? ports p7 4 , p7 5 pull- up control 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 0: no pull-up 1: pull-up 6 0 ports p9 0 , p9 1 pull- up control 0: no pull-up 1: pull-up note: the pin set to output port is cut off from pull-up control. pins p1, p3 p5, p6 1 Cp6 5 , p7, p8 4 Cp8 7 , p9 p4 0 Cp4 6 , p6 0 p0, p2, p8 0 Cp8 3 p4 7 v ref x out av ss , v ee termination open at h output state. ? set to the input mode and connect each to v cc or v ss through a resistor of 1 k w to 10 k w . ? set to the output mode and open at l or h output state. ? set to the input mode and connect each to v cc or v ss through a resistor of 1 k w to 10 k w . ? set to the output mode and open at l output state. ? set to the input mode and connect each to v cc or v ss through a resistor of 1 k w to 10 k w . ? set to the output mode and open at h output state. disable int 2 interrupt and connect to v cc or v ss through a resistor of 1 k w to 10 k w . open open (only when using external clock) connect to v ss (gnd).
2-7 application 2.1 i/o port 38b5 group users manual 2.1.4 notes on use (1) notes in standby state in standby state ] 1 for low-power dissipation, do not make input levels of an input port and an i/o port undefined, especially for i/o ports of the p-channel open-drain and the n-channel open-drain. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: ? external circuit ? variation of output levels during the ordinary operation when using built-in pull-up resistor, note on varied current values: ? when setting as an input port : fix its input level ? when setting as an output port : prevent current from flowing out to external l reason even when setting as an output port with its direction register, in the following state : ? p-channel......when the content of the port latch is 0 ? n-channel......when the content of the port latch is 1 the transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes undefined depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an i/o port are undefined. this may cause power source current. ] 1 standby state: stop mode by executing stp instruction wait mode by executing wit instruction (2) n-channel open-drain port p4 0 Cp4 2 , p4 5 , p4 6 , p6 0 of n-channel open-drain output ports have the built-in hysteresis circuit for input. in standby state for low-power dissipation, do not make these pins floating state. l reason when power sources for pull-up of these pins are cut off in standby state, these ports become floating. accordingly, a current may flow from vcc to vss through the built-in hysteresis circuit.
2-8 38b5 group users manual application 2.1 i/o port (3) modifying port latch of i/o port with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction ] 2 , the value of the unspecified bit may be changed. l reason the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. ?as for bit which is set for input port: the pin state is read in the cpu, and is written to this bit after bit managing. ?as for bit which is set for output port: the bit value is read in the cpu, and is written to this bit after bit managing. note the following: ?even when a port which is set as an output port is changed for an input port, its port latch holds the output data. ?as for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. ] 2 bit managing instructions: seb and clb instructions (4) pull-up control when each port which has built-in pull-up resistor (p5, p6 1 Cp6 5 , p7, p8 4 Cp8 7 , p9) is set to output port, pull-up control of corresponding port become invalid. (pull-up cannot be set.) l reason pull-up control is valid only when each direction register is set to the input mode. 2.1.5 termination of unused pins (1) terminate unused pins output ports : open input ports : connect each pin to v cc or v ss through each resistor of 1 k w to 10 k w . as for pins whose potential affects to operation modes such as pin int or others, select the v cc pin or the v ss pin according to their operation mode. a i/o ports : ? set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k w to 10 k w . ports that permit the selecting of a built-in pull-up resistor can also use this resistor. set the i/o ports for the output mode and open them at l or h. ? when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. ? since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program.
2-9 application 2.1 i/o port 38b5 group users manual (2) termination remarks input ports and i/o ports : do not open in the input mode. l reason ? the power source current may increase depending on the first-stage circuit. ? an effect due to noise may be easily produced as compared with proper termination and a shown on the above. i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. l reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). a i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. l reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. ? at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
2-10 38b5 group user? manual application 2.2 timer 2.2 timer this paragraph explains the registers setting method and the notes relevant to the timers. 2.2.1 memory map fig. 2.2.1 memory map of registers relevant to timers 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 5 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 c 1 6 t i m e r 1 ( t 1 ) t i m e r 4 ( t 4 ) t i m e r 6 ( t 6 ) t i m e r 6 p w m r e g i s t e r ( t 6 p w m ) t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m ) t i m e r x ( l o w - o r d e r ) ( t x l ) 0 0 3 e 1 6 0 0 3 f 1 6 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) 0 0 2 0 1 6 0 0 2 1 1 6 t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) 0 0 2 4 1 6 t i m e r 5 ( t 5 ) t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) 0 0 2 9 1 6 t i m e r 5 6 m o d e r e g i s t e r ( t 5 6 m ) 0 0 2 a 1 6 0 0 2 d 1 6 t i m e r x ( h i g h - o r d e r ) ( t x h ) 0 0 2 e 1 6 t i m e r x m o d e r e g i s t e r 1 ( t x m 1 ) 0 0 2 f 1 6 t i m e r x m o d e r e g i s t e r 2 ( t x m 2 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) 0 0 3 d 1 6 0 0 3 c 1 6
38b5 group users manual application 2-11 2.2 timer fig. 2.2.3 structure of timer 2 fig. 2.2.4 structure of timer 6 pwm register fig. 2.2.2 structure of timer i (i=1, 3, 4, 5, 6) timer i b7 b6 b5 b4 b3 b2 b1 b0 timer i (i = 1, 3, 4, 5, 6) (ti: addresses 20 16 , 22 16 , 23 16 , 24 16 , 25 16 ) b 0 1 at reset r w 1 2 3 4 5 6 7 functions ?set timer i count value. ?the value set in this register is written to both the timer i and the timer i latch at one time. ?when the timer i is read out, the count value of the timer i is read out. 1 1 1 1 1 1 1 timer 2 b7 b6 b5 b4 b3 b2 b1 b0 timer 2 (t2: address 21 16 ) b 0 1 at reset r w 1 2 3 4 5 6 7 functions ?set timer 2 count value. ?the value set in this register is written to both the timer 2 and the timer 2 latch at one time. ?when the timer 2 is read out, the count value of the timer 2 is read out. 0 0 0 0 0 0 0 timer 6 pwm register b7 b6 b5 b4 b3 b2 b1 b0 timer 6 pwm register (t6pwm: address 27 16 ) b 0 1 2 3 4 5 6 7 undefined functions at reset r w undefined undefined undefined undefined undefined undefined undefined ?in timer 6 pwm 1 mode ??level width of pwm rectangular waveform is set. ?duty of pwm rectangular waveform: n/(n + m) period: (n + m) ts n = timer 6 set value m = timer 6 pwm register set value ts = timer 6 count source period at n = 0, all pwm output ?? at m = 0, all pwm output ?? (however, n = 0 has priority.) ?selection of timer 6 pwm 1 mode set ??to the timer 6 operation mode selection bit. 2.2.2 relevant registers (1) 8-bit timer
2-12 38b5 group users manual application 2.2 timer fig. 2.2.5 structure of timer 12 mode register timer 12 mode register b7 b6 b5 b4 b3 b2 b1 b0 timer 12 mode register (t12m: address 28 16 ) 0: count operation 1: count stop b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0: count operation 1: count stop 0 0 0: f(x in )/8 or f(x cin )/16 0 1: f(x cin ) 1 0: f(x in )/16 or f(x cin )/32 1 1: f(x in )/64 or f(x cin )/128 0 0 0 0: i/o port 1: timer 1 output 0 0 timer 1 count stop bit timer 2 count stop bit timer 2 count source selection bits timer 1 output selection bit (p4 5 ) timer 1 count source selection bits nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? b3 b2 b5 b4 0 0: timer 1 underflow 0 1: f(x cin ) 1 0: external count input cntr 0 1 1: not available fig. 2.2.6 structure of timer 34 mode register timer 34 mode register b7 b6 b5 b4 b3 b2 b1 b0 timer 34 mode register (t34m: address 29 16 ) 0: count operation 1: count stop b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0: count operation 1: count stop 0 0 0: f(x in )/8 or f(x cin )/16 0 1: timer 2 underflow 1 0: f(x in )/16 or f(x cin )/32 1 1: f(x in )/64 or f(x cin )/128 0 0 0 0: i/o port 1: timer 3 output 0 0 timer 3 count stop bit timer 4 count stop bit timer 4 count source selection bits timer 3 output selection bit (p4 6 ) timer 3 count source selection bits nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? b3 b2 b5 b4 0 0: f(x in )/8 or f(x cin )/16 0 1: timer 3 underflow 1 0: external count input cntr 1 (note) 1 1: not available note: in the mask option type p, cntr 1 function cannot be used.
38b5 group users manual application 2-13 2.2 timer fig. 2.2.7 structure of timer 56 mode register (2) 16-bit timer timer 56 mode register b7 b6 b5 b4 b3 b2 b1 b0 timer 56 mode register (t56m: address 2a 16 ) 0: count operation 1: count stop b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0: count operation 1: count stop 0 0: f(x in )/8 or f(x cin )/16 1: timer 4 underflow 0: timer mode 1: pwm mode 0 0 0 0: i/o port 1: timer 6 output 0 0 0 timer 5 count stop bit timer 6 count stop bit timer 6 count source selection bits timer 6 (pwm) output selection bit (p4 4 ) timer 5 count source selection bit timer 6 operation mode selection bit nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? b5 b4 0 0: f(x in )/8 or f(x cin )/16 0 1: timer 5 underflow 1 0: timer 4 underflow 1 1: not available fig. 2.2.8 structure of timer x (low-order, high-order) timer x (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 timer x (low-order, high-order) (txl, txh: addresses 2c 16 , 2d 16 ) b 0 1 2 3 4 5 6 7 1 functions at reset r w 1 1 1 1 1 1 1 ?set timer x count value. ?when the timer x write control bit of the timer x mode register 1 is ?? the value is written to timer x and the latch at one time. when the timer x write control bit of the timer x mode register 1 is ?? the value is written only to the latch. ?the timer x count value is read out by reading this register. notes 1: when reading and writing, perform them to both the high- order and low-order bytes. 2: read both registers in order of txh and txl following. 3: write both registers in order of txl and txh following. 4: do not read both registers during a write, and do not write to both registers during a read.
2-14 38b5 group users manual application 2.2 timer fig. 2.2.9 structure of timer x mode register 1 timer x mode register 1 b7 b6 b5 b4 b3 b2 b1 b0 timer x mode register 1 (txm1: address 2e 16 ) b 0 name 0 functions at reset r w timer x write control bit 0 : write value in latch and counter 1 : write value in latch only 1 0 2 0 3 0 7 0 timer x stop control bit 0 : count operating 1 : count stop 6 0 cntr 2 active edge switch bit 0 : ?ount at rising edge in event counter mode ?tart from ??output in pulse output mode ?easure ??pulse width in pulse width measurement mode 1 : ?ount at falling edge in event counter mode ?tart from ??output in pulse output mode ?easure ??pulse width in pulse width measurement mode 4 5 0 0 timer x operating mode bits b5 b4 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode timer x count source selection bits 0 0: f(x in )/2 or f(x cin )/4 0 1: f(x in )/8 or f(x cin )/16 1 0: f(x in )/64 or f(x cin )/128 1 1: not available b2 b1 nothing is arranged for this bit. this is write disabled bit. when this bit is read out, the contents are ??
38b5 group user? manual application 2-15 2.2 timer fig. 2.2.10 structure of timer x mode register 2 timer x mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 timer x mode register 2 (txm2: address 2f 16 ) b 0 2 4 name 0 functions at reset r w 0 nothing is arranged for these bits. these are write disabled bits. when these bits are read out, the contents are ?? real time port control bit (p8 5 ) real time port control bit (p8 6 ) 0: real time port function is invalid 1: real time port function is valid 0 0 0: real time port function is invalid 1: real time port function is valid 1 p8 5 data for real time port 0: ??output 1: ??output 3 0 0 p8 6 data for real time port 0: ??output 1: ??output 0 0 0 5 6 7
2-16 38b5 group users manual application 2.2 timer fig. 2.2.11 structure of interrupt request register 1 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1 : address 3c 16 ) b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 0 0 0 0 0 int 0 interrupt request bit int 1 interrupt request bit serial i/o1 interrupt request bit serial i/o automatic transfer interrupt request bit timer x interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit int 2 interrupt request bit remote controller /counter overflow interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued timer 3 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 ] ] ] ] ] ] ] ] ] : ??can be set by software, but ??cannot be set. (3) 8-bit timer, 16-bit timer
38b5 group users manual application 2-17 2.2 timer fig. 2.2.12 structure of interrupt request register 2 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2 : address 3d 16 ) b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 0 0 0 0 0 timer 4 interrupt request bit (note) timer 5 interrupt request bit serial i/o2 receive interrupt request bit int 3 /serial i/o2 transmit interrupt request bit (note) int 4 interrupt request bit a-d converter interrupt request bit fld blanking interrupt request bit fld digit interrupt request bit timer 6 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 ] ] ] ] ] ] ] nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? ] : ??can be set by software, but ??cannot be set. note: in the mask option type p, if timer 4 interrupt whose count source is cntr 1 input and int 3 interrupt are selected, these bits do not become ?? 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued
2-18 38b5 group users manual application 2.2 timer fig. 2.2.14 structure of interrupt control register 2 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2 : address 3f 16 ) b 0 0 1 2 3 4 name 0 functions at reset r w 0 0 0 0 timer 5 interrupt enable bit serial i/o2 receive interrupt enable bit int 3 /serial i/o2 transmit interrupt enable bit (note) timer 6 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 5 0 int 4 interrupt enable bit a-d converter interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 6 7 0 fld blanking interrupt enable bit fld digit interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 fix ??to this bit. timer 4 interrupt enable bit (note) note: in the mask option type p, timer 4 interrupt whose count source is cntr 1 input and int 3 interrupt are not available. 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1 : address 3e 16 ) b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 0 0 0 int 0 interrupt enable bit int 1 interrupt enable bit serial i/o1 interrupt enable bit serial i/o automatic transfer interrupt enable bit timer x interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit int 2 interrupt enable bit remote controller /counter overflow interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 3 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 fig. 2.2.13 structure of interrupt control register 1
38b5 group users manual application 2-19 2.2 timer 2.2.3 timer application examples (1) basic functions and uses [function 1] control of event interval (timer 1 to timer 6, timer x: timer mode) when a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. |
